Invention Grant
- Patent Title: Multi-page parity data storage in a memory device
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Application No.: US18098279Application Date: 2023-01-18
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Publication No.: US11928353B2Publication Date: 2024-03-12
- Inventor: Harish R Singidi , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Kishore Kumar Muchherla
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F11/10 ; H03M7/30

Abstract:
A processing device, operatively coupled with a memory device, is configured to perform a write operation on a page of a plurality of pages of a data unit of a memory device. The processing device further generates a parity page for data stored in the page of the data unit and associates the parity page with parity data associated with the data unit. Responsive to determining that a first size of the parity data is larger than a first threshold size, the processing device compresses the parity data. Responsive to determining that a second size of the compressed parity data is larger than a second threshold size, the processing device releases at least a subset of the parity data corresponding to a subset of the data that is free from defects.
Public/Granted literature
- US20230153011A1 MULTI-PAGE PARITY DATA STORAGE IN A MEMORY DEVICE Public/Granted day:2023-05-18
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