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公开(公告)号：US20240329852A1
公开(公告)日：2024-10-03
申请号：US18739982
申请日：2024-06-11
发明人： Li-Te Chang , Murong Lang , Charles See Yeung Kwong , Vamsi Pavan Rayaprolu , Seungjune Jeon , Zhenming Zhou
CPC分类号： G06F3/0616 , G06F3/0653 , G06F3/0679 , G06N20/00
摘要： A processing device in a memory sub-system determines one or more read margin levels associated with the memory device. A machine learning model is applied to the one or more read margin levels to generate a read margin prediction value associated with the memory device. Based on the margin prediction value, the memory device is assigned to a selected bin of a set of bins. A media scan operation is executed on the memory device in accordance with a scan frequency associated with the selected bin.
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公开(公告)号：US12072762B2
公开(公告)日：2024-08-27
申请号：US17884076
申请日：2022-08-09
CPC分类号： G06F11/1044 , G11C29/08
摘要： Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; responsive to determining that a data integrity metric value satisfies the threshold criterion, performing a first error-handling operation on the data stored on the source set of memory cells; responsive to determining that the first error-handling operation fails to correct the data, performing a second error-handling operation on the data; and responsive to determining that the second error-handling operation corrected the data, causing the memory device to copy the corrected data to a destination set of memory cells of the memory device.
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公开(公告)号：US20240256145A1
公开(公告)日：2024-08-01
申请号：US18634347
申请日：2024-04-12
IPC分类号： G06F3/06
CPC分类号： G06F3/0616 , G06F3/0653 , G06F3/0679
摘要： A memory system includes a memory device and a processing device, operatively coupled to the memory device. The processing device performs operations comprising: identifying one or more mandatory scan wordlines of the memory device and one or more remaining wordlines of the memory device; performing a plurality of scan iterations with respect to a plurality of pages of the memory device, such that performing each scan iteration comprises: identifying, among the remaining wordlines, one or more scheduled scan wordlines of the memory device, scanning a subset of pages of the memory device that are addressable by the mandatory scan wordlines and the scheduled scan wordlines; wherein a combination of a first plurality of pages addressable by the scheduled scan wordlines selected by the plurality of scan iterations and a second plurality of pages addressable by the mandatory wordlines comprises the plurality of pages of the memory device.
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公开(公告)号：US12050777B2
公开(公告)日：2024-07-30
申请号：US17880213
申请日：2022-08-03
发明人： Li-Te Chang , Murong Lang , Charles See Yeung Kwong , Vamsi Pavan Rayaprolu , Seungjune Jeon , Zhenming Zhou
CPC分类号： G06F3/0616 , G06F3/0653 , G06F3/0679 , G06N20/00
摘要： A processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. In response to the one or more conditions being satisfied, one or more read margin levels corresponding to a page type associated with the memory device are determined. A machine learning model is applied to the one or more read margin levels to generate a margin prediction value based on the page type and a wordline group associated with the memory device. Based on the margin prediction value, the memory device is assigned to a selected bin of a set of bins. A media scan operation is executed on the memory device in accordance with a scan frequency associated with the selected bin.
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公开(公告)号：US12032833B2
公开(公告)日：2024-07-09
申请号：US17943082
申请日：2022-09-12
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0655 , G06F3/0679
摘要： Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including running sample data through each of a set of error-handling operations performed on data residing in a segment of the memory device in an existing order associated with a workload; obtaining error recovery data as a result of running the sample data; and determining an optimized order of the set of error-handling operations based on probability of error recovery and latency data, wherein the probability of error recovery is based on the error recovery data, and wherein the optimized order comprises an adjustment to an order of one or more error-handling operations of the set of error-handling operations in the existing order.
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公开(公告)号：US20240111445A1
公开(公告)日：2024-04-04
申请号：US18526634
申请日：2023-12-01
发明人： Michael Sheperek , Kishore Kumar Muchherla , Mustafa N. Kaynak , Vamsi Pavan Rayaprolu , Bruce A. Liikanen , Peter Feeley , Larry J. Koudele , Shane Nowell , Steven Michael Kientz
CPC分类号： G06F3/064 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06F12/10 , G11C16/26 , G11C16/0483
摘要： An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.
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7.发明公开公开(公告)号：US20240103749A1
公开(公告)日：2024-03-28
申请号：US18526103
申请日：2023-12-01
发明人： Sampath K. Ratnam , Vamsi Pavan Rayaprolu , Mustafa N. Kaynak , Sivagnanam Parthasarathy , Kishore Kumar Muchherla , Shane Nowell , Peter Feeley , Qisong Lin
CPC分类号： G06F3/0647 , G06F3/0619 , G06F3/0673 , G06F11/1068 , G06F11/1402 , G11C29/52
摘要： At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.
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公开(公告)号：US11934266B2
公开(公告)日：2024-03-19
申请号：US17859468
申请日：2022-07-07
发明人： Vamsi Pavan Rayaprolu , Mustafa N. Kaynak , Sivagnanam Parthasarathy , Patrick Khayat , Sampath Ratnam , Kishore Kumar Muchherla , Jiangang Wu , James Fitzpatrick
CPC分类号： G06F11/1068 , G06F11/076 , G06F11/0772
摘要： Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, wherein the source set of memory cells are configured to store a first number of bits per memory cell; performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell.
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公开(公告)号：US20240086316A1
公开(公告)日：2024-03-14
申请号：US18519311
申请日：2023-11-27
IPC分类号： G06F12/02 , G06F3/06 , G06F12/0882
CPC分类号： G06F12/0246 , G06F3/0614 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F12/0882 , G06F2212/7201
摘要： A system includes a memory device and a processing device communicatively coupled to the memory device. The processing device is to write data to a number of groups of memory cells of the memory device in a physically non-contiguous manner. The processing device is further to track a sequence in which the number of groups of memory cells were written with the data. In response to a trigger event, the processing device is further to identify at least a portion of the number of groups of memory cells having data received over a predefined period preceding the trigger event based at least in part on the tracked sequence.
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公开(公告)号：US11928353B2
公开(公告)日：2024-03-12
申请号：US18098279
申请日：2023-01-18
CPC分类号： G06F3/0652 , G06F3/0608 , G06F3/0679 , G06F11/1004 , H03M7/6011
摘要： A processing device, operatively coupled with a memory device, is configured to perform a write operation on a page of a plurality of pages of a data unit of a memory device. The processing device further generates a parity page for data stored in the page of the data unit and associates the parity page with parity data associated with the data unit. Responsive to determining that a first size of the parity data is larger than a first threshold size, the processing device compresses the parity data. Responsive to determining that a second size of the compressed parity data is larger than a second threshold size, the processing device releases at least a subset of the parity data corresponding to a subset of the data that is free from defects.
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