Invention Grant
- Patent Title: Damascene process using cap layer
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Application No.: US16885278Application Date: 2020-05-28
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Publication No.: US11929329B2Publication Date: 2024-03-12
- Inventor: Chia-Cheng Chou , Chung-Chi Ko , Tze-Liang Lee , Ming-Tsung Lee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/532

Abstract:
A semiconductor device including a substrate, a low-k dielectric layer, a cap layer, and a conductive layer is provided. The low-k dielectric layer is disposed over the substrate. The cap layer is disposed on the low-k dielectric layer, wherein a carbon atom content of the cap layer is greater than a carbon atom content of the low-k dielectric layer. The conductive layer is disposed in the cap layer and the low-k dielectric layer.
Public/Granted literature
- US20210375779A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Public/Granted day:2021-12-02
Information query
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