Invention Grant
- Patent Title: Memory command aggregation to improve sequential memory command performance
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Application No.: US17492143Application Date: 2021-10-01
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Publication No.: US11934676B2Publication Date: 2024-03-19
- Inventor: Naveen Bolisetty , Peng Fei , Yiran Liu , Shakeel Bukhari
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee Address: US ID Boise
- Agency: NICHOLSON DE VOS WEBSTER & ELLIOTT LLP
- Priority: WO TCN2021107663 2021.07.21
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
A method is described, which includes receiving, by a memory subsystem controller from a host system, a host read memory command that references a set of logical block addresses associated with a set of transfer units of a memory device. The controller converts the set of logical block addresses to a set of physical block addresses for the set of transfer units; generates a set of device read memory commands based on the physical block addresses, wherein each device read memory command references at least one physical block address; and generates a first aggregated device read memory command based on a first device read memory command and a second read memory command in response to determining that the first device read memory command is associated with the second device read memory command. The controller thereafter transmits the first aggregated device read memory command to the memory device.
Public/Granted literature
- US20230025508A1 MEMORY COMMAND AGGREGATION TO IMPROVE SEQUENTIAL MEMORY COMMAND PERFORMANCE Public/Granted day:2023-01-26
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