Invention Grant
- Patent Title: Bottom implant and airgap isolation for nanosheet semiconductor devices
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Application No.: US17480482Application Date: 2021-09-21
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Publication No.: US11948832B2Publication Date: 2024-04-02
- Inventor: Yan Zhang , Johannes M. van Meer , Naushad K. Variam
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: KDW Firm PLLC
- Main IPC: H01L21/764
- IPC: H01L21/764 ; H01L21/8238 ; H01L27/092

Abstract:
A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.
Public/Granted literature
- US20230089482A1 BOTTOM IMPLANT AND AIRGAP ISOLATION FOR NANOSHEET SEMICONDUCTOR DEVICES Public/Granted day:2023-03-23
Information query
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