公开(公告)号：US20240266175A1

公开(公告)日：2024-08-08

申请号：US18105302

申请日：2023-02-03

Applicant: Applied Materials, Inc.

Inventor： Yan Zhang ,  Johannes M. van Meer ,  Jae Young Lee ,  Naushad Variam

IPC: H01L21/265 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L21/26506 ,  H01L21/30625 ,  H01L21/76898

Abstract: A method of processing a workpiece that will include a backside power delivery network is disclosed. The method includes forming a CMP marker layer in the workpiece at the depth to which the workpiece is to be thinned. This CMP marker layer, which may be a boron-rich layer, serves to slow the chemical-mechanical planarization (CMP) process. To minimize the diffusion of boron in this boron-rich layer, the boron-rich layer is sandwiched by implants of a first species of ions, where this first species of ions serves to slow the diffusion of the boron. In certain embodiments, carbon is used as the first species of ions.

公开(公告)号：US20230187210A1

公开(公告)日：2023-06-15

申请号：US17548002

申请日：2021-12-10

Applicant: Applied Materials, Inc.

Inventor： Yan Zhang ,  Johannes M. van Meer ,  Naushad K. Variam

IPC: H01L21/265 ,  H01L29/66

CPC classification number: H01L21/265 ,  H01L29/66545 ,  H01L29/66553

Abstract: Approaches herein provide devices and methods for forming optimized gate-all-around transistors. One method may include forming a well by directing a first ion species into a substrate of a device, forming a plurality of alternating first and second layers over the well, and forming a dummy gate and a spacer over the plurality of alternating first and second layers. The method may further include removing a portion of the plurality of alternating first and second layers to expose an upper surface of the well, forming a punch through stopper in the well by directing a second ion species into the exposed upper surface of the well, etching the plurality of nanosheets to laterally recess the second layers relative to the first layers, and forming an inner spacer along the first and second layers.

公开(公告)号：US20220399225A1

公开(公告)日：2022-12-15

申请号：US17348093

申请日：2021-06-15

Applicant: Applied Materials, Inc.

Inventor： Armin Saeedi Vahdat ,  Tristan Y. Ma ,  Johannes M. van Meer ,  John Hautala ,  Naushad K. Variam

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/764

Abstract: Disclosed are approaches for forming semiconductor device cavities using directional dielectric deposition. One method may include providing a plurality of semiconductor structures and a plurality of trenches of a semiconductor device, and forming a dielectric atop the plurality of semiconductor structures by delivering a dielectric material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the plurality of semiconductor structures. The dielectric may be further formed by delivering the dielectric material at a second non-zero angle of inclination relative to the normal extending perpendicular from the top surface of the plurality of semiconductor structures.

公开(公告)号：US20220068715A1

公开(公告)日：2022-03-03

申请号：US17006428

申请日：2020-08-28

Applicant: Applied Materials, Inc.

Inventor： Andrew Michael Waite ,  Johannes M. van Meer ,  Jae Young Lee

IPC: H01L21/8234 ,  H01L21/26

Abstract: In one embodiment, a method may include providing a substrate, comprising a plurality of surface features, an isolation layer, disposed between the plurality of surface features, and a substrate base, disposed subjacent the isolation layer and the plurality of surface features, wherein the plurality of surface features extend above a surface of the isolation layer. The method may include directing a low energy ion beam to the substrate, when the substrate is heated at a targeted temperature, wherein an altered layer is formed within an outer portion of the isolation layer, and wherein an inner portion of the isolation layer is not implanted.

公开(公告)号：US20210366776A1

公开(公告)日：2021-11-25

申请号：US16879134

申请日：2020-05-20

Applicant: Applied Materials, Inc.

Inventor： Min Gyu Sung ,  Johannes M. van Meer

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/3115

Abstract: Disclosed are approaches for forming finFET devices having asymmetric fins achieved via fin trimming. In some embodiments, a method may include providing a substrate within a process chamber, the substrate including a plurality of fins, and forming a capping layer over the plurality of fins, wherein the capping layer extends along a first sidewall and a second sidewall of each of the plurality of fins. The method may further include removing a portion of the capping layer to expose a target area of the first sidewall of each of the plurality of fins, and trimming the target area of the first sidewall of each of the plurality of fins to reduce a lateral width of an upper section of each of the plurality of fins.

公开(公告)号：US11948832B2

公开(公告)日：2024-04-02

申请号：US17480482

申请日：2021-09-21

Applicant: Applied Materials, Inc.

Inventor： Yan Zhang ,  Johannes M. van Meer ,  Naushad K. Variam

IPC: H01L21/764 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/764 ,  H01L21/823878 ,  H01L27/092

Abstract: A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.

公开(公告)号：US20240049443A1

公开(公告)日：2024-02-08

申请号：US17881969

申请日：2022-08-05

Applicant: Applied Materials, Inc.

Inventor： Armin Saeedi Vahdat ,  John Hautala ,  Yan Zhang ,  Johannes M. van Meer

IPC: H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10823

Abstract: Approaches for reducing GIDL are disclosed. In one example, a method of forming a DRAM device may include forming a trench in a substrate layer, providing a first gate oxide layer along a sidewall and a bottom surface of the trench, and forming a first gate material within the trench. The method may further include removing the first gate oxide layer along an upper portion of the sidewall of the trench by delivering ions into the upper portion of the trench at a non-zero angle relative to a perpendicular extending from an upper surface of the substrate layer, and forming a second gate oxide layer along the upper portion of the sidewall of the trench, wherein a first dielectric constant of the first gate oxide layer is greater than a second dielectric constant of the second gate oxide layer.

公开(公告)号：US20230369453A1

公开(公告)日：2023-11-16

申请号：US17744238

申请日：2022-05-13

Applicant: Applied Materials, Inc.

Inventor： Yan Zhang ,  Johannes M. van Meer ,  Sankuei Lin ,  Baonian Guo ,  Naushad K. Variam

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/40

CPC classification number: H01L29/66545 ,  H01L29/66553 ,  H01L29/42392 ,  H01L29/0665 ,  H01L29/78696 ,  H01L29/401

Abstract: A method for forming a nanosheet device. The method may include providing a heterostructure device stack above a semiconductor substrate. The method may include patterning the heterostructure device stack to define a dummy gate region, and before forming a source drain recess adjacent the dummy gate region, selectively removing a first set of sacrificial layers of the heterostructure device stack within the dummy gate region.

公开(公告)号：US11424164B2

公开(公告)日：2022-08-23

申请号：US17006428

申请日：2020-08-28

Applicant: Applied Materials, Inc.

Inventor： Andrew Michael Waite ,  Johannes M. van Meer ,  Jae Young Lee

IPC: H01L21/8234 ,  H01L21/26

Abstract: In one embodiment, a method may include providing a substrate, comprising a plurality of surface features, an isolation layer, disposed between the plurality of surface features, and a substrate base, disposed subjacent the isolation layer and the plurality of surface features, wherein the plurality of surface features extend above a surface of the isolation layer. The method may include directing a low energy ion beam to the substrate, when the substrate is heated at a targeted temperature, wherein an altered layer is formed within an outer portion of the isolation layer, and wherein an inner portion of the isolation layer is not implanted.

公开(公告)号：US20220108886A1

公开(公告)日：2022-04-07

申请号：US17150781

申请日：2021-01-15

Applicant: Applied Materials, Inc.

Inventor： Keith T. Wong ,  Hurshvardhan Srivastava ,  Srinivas D. Nemani ,  Johannes M. van Meer ,  Rajesh Prasad

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/24 ,  H01L29/76 ,  C23C16/30 ,  C23C16/455 ,  C23C16/56 ,  C23C14/48 ,  C23C14/58

Abstract: A method to form a 2-Dimensional transistor channel may include depositing an amorphous layer comprising a 2-dimensional material, implanting an implant species into the amorphous layer; and annealing the amorphous layer after the implanting. As such, the amorphous layer may form a doped crystalline layer.