Invention Grant
- Patent Title: Semiconductor package and method of fabricating the same
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Application No.: US17509224Application Date: 2021-10-25
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Publication No.: US11948872B2Publication Date: 2024-04-02
- Inventor: Jongyoun Kim , Minjun Bae , Hyeonseok Lee , Gwangjae Jeon
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce, P.L.C.
- Priority: KR 20210037518 2021.03.23
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31 ; H01L23/498 ; H01L25/18 ; H01L23/34

Abstract:
Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.
Public/Granted literature
- US20220310496A1 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME Public/Granted day:2022-09-29
Information query
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