公开(公告)号：US20240071894A1

公开(公告)日：2024-02-29

申请号：US18335336

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong Hwang ,  Dongkyu Kim ,  Kyounglim Suk ,  Hyeonseok Lee

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227

Abstract: A packaged integrated circuit includes a redistribution layer having a plurality of electrically conductive vias extending at least partially therethrough, and a plurality of lower pads electrically connected to corresponding ones of the plurality of electrically conductive vias. A semiconductor chip is provided on the redistribution layer, and external connection terminals are provided, which electrically contact corresponding ones of the plurality of lower pads within the redistribution layer. Each of the plurality of lower pads includes: (i) a lower under-bump metallization (UBM) layer in contact with a corresponding external connection terminal, and (ii) an upper UBM layer extending on and contacting the lower UBM layer. In addition, an upper surface of the lower UBM layer has a greater lateral width dimension relative to an upper surface of the upper UBM layer, which contacts a corresponding electrically conductive via.

公开(公告)号：US12230556B2

公开(公告)日：2025-02-18

申请号：US18588699

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Minjun Bae ,  Hyeonseok Lee ,  Gwangjae Jeon

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18 ,  H01L23/34

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.

公开(公告)号：US20240006262A1

公开(公告)日：2024-01-04

申请号：US18176695

申请日：2023-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon MUN ,  Eungkyu Kim ,  Hyeonseok Lee

IPC: H01L23/367 ,  H01L25/16 ,  H10B80/00 ,  H01L23/498 ,  H01L23/373

CPC classification number: H01L23/3677 ,  H01L25/165 ,  H10B80/00 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/3738 ,  H01L24/16

Abstract: A semiconductor package includes a first redistribution structure, a first die above the first redistribution structure, a second die above the first die, a heat dissipation unit on side surfaces of the first die or the second die, and a second redistribution structure above the second die. The semiconductor package includes a first post protruding from an upper surface of the first redistribution structure and extending to a lower surface of the second redistribution structure, a second post connecting the heat dissipation unit with a heat dissipation redistribution structure as a thermal path, and a molding unit filling an empty space between the first redistribution structure and the second redistribution structure. An outer pad of the heat dissipation redistribution structure is exposed to an outside of the semiconductor package, and an inner pad of the heat dissipation redistribution structure is in contact with the second post.

公开(公告)号：US12057435B2

公开(公告)日：2024-08-06

申请号：US17723981

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonseok Lee ,  Jongyoun Kim ,  Seokhyun Lee

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065

CPC classification number: H01L25/0655 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/13008 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/13541 ,  H01L2224/13553 ,  H01L2224/1357 ,  H01L2224/16014 ,  H01L2224/16055 ,  H01L2224/16058 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17055 ,  H01L2924/182

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces, a first semiconductor chip on the first surface, external terminals on the second surface, a second semiconductor chip above the first semiconductor chip, external connection members below the second semiconductor chip, conductive pillars electrically connecting the external connection members to the redistribution substrate. The second semiconductor chip includes a device layer, a wiring layer, and a redistribution layer on a semiconductor substrate. The wiring layer includes intermetallic dielectric layers, wiring lines, and a conductive pad connected to an uppermost wiring line. The redistribution layer includes a first redistribution dielectric layer, a first redistribution pattern, and a second redistribution dielectric layer. A vertical distance between the semiconductor substrate and the conductive pillars is less than that between the first semiconductor chip and the external terminals.

公开(公告)号：US11948872B2

公开(公告)日：2024-04-02

申请号：US17509224

申请日：2021-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Minjun Bae ,  Hyeonseok Lee ,  Gwangjae Jeon

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18 ,  H01L23/34

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/18 ,  H01L23/34 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/73204

Abstract: Disclosed are semiconductor packages and their fabricating methods. The semiconductor package comprises a redistribution substrate, a semiconductor chip on a top surface of the redistribution substrate, and a solder terminal on a bottom surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern in contact with the solder terminal, a dielectric layer on a sidewall of the under-bump pattern, an under-bump seed pattern between the dielectric layer and the sidewall of the under-bump pattern, and a redistribution pattern on the under-bump pattern. The under-bump pattern has central and edge regions. A first top surface at the edge region of the under-bump pattern is at a level higher than that of a second top surface at the central region of the under-bump pattern. An angle between the bottom surface and the sidewall of the under-bump pattern is in a range of 110° to 140°.