Invention Grant
- Patent Title: Semiconductor apparatus examination method and semiconductor apparatus examination apparatus
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Application No.: US17607155Application Date: 2020-05-19
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Publication No.: US11967061B2Publication Date: 2024-04-23
- Inventor: Hirotoshi Terada , Yoshitaka Iwaki
- Applicant: HAMAMATSU PHOTONICS K.K.
- Applicant Address: JP Hamamatsu
- Assignee: HAMAMATSU PHOTONICS K.K.
- Current Assignee: HAMAMATSU PHOTONICS K.K.
- Current Assignee Address: JP Hamamatsu
- Agency: Faegre Drinker Biddle & Reath LLP
- Priority: JP 19128344 2019.07.10
- International Application: PCT/JP2020/019811 2020.05.19
- International Announcement: WO2021/005892A 2021.01.14
- Date entered country: 2021-10-28
- Main IPC: G06V10/00
- IPC: G06V10/00 ; G06T7/00 ; G06T7/70 ; G06T11/00

Abstract:
A semiconductor apparatus examination method includes a step of detecting light from a plurality of positions in a semiconductor apparatus (D) and acquiring a waveform corresponding to each of the plurality of positions, a step of extracting a waveform corresponding to a specific timing from the waveform corresponding to each of the plurality of positions and generating an image corresponding to the specific timing based on the extracted waveform, and a step of extracting a feature point based on a brightness distribution correlation value in the image corresponding to the specific timing and identifying a position of a drive element in the semiconductor apparatus based on the feature point.
Public/Granted literature
- US20220207710A1 SEMICONDUCTOR APPARATUS EXAMINATION METHOD AND SEMICONDUCTOR APPARATUS EXAMINATION APPARATUS Public/Granted day:2022-06-30
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