Invention Grant
- Patent Title: Memory circuit using oxide semiconductor
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Application No.: US17618993Application Date: 2020-06-09
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Publication No.: US11996133B2Publication Date: 2024-05-28
- Inventor: Fumika Akasawa , Munehiro Kozuma
- Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
- Applicant Address: JP Atsugi
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Kanagawa-ken
- Agency: NIXON PEABODY LLP
- Agent Jeffrey L. Costellia
- Priority: JP 19115553 2019.06.21
- International Application: PCT/IB2020/055394 2020.06.09
- International Announcement: WO2020/254914A 2020.12.24
- Date entered country: 2021-12-14
- Main IPC: G11C11/40
- IPC: G11C11/40 ; G11C11/405 ; H01L27/12 ; H01L29/786 ; H10B12/00

Abstract:
Since power source voltages are different depending on circuits used for devices, a circuit for outputting at least two or more power sources is additionally prepared. An object is to unify outputs of the power source voltages. A transistor using an oxide semiconductor is provided in such a manner that electrical charge is retained in a node where the transistor and a capacitor are electrically connected to each other, a reset signal is applied to a gate of the transistor to switch the states of the transistor from off to on, and the node is reset when the transistor is on. A circuit configuration that generates and utilizes a potential higher than or equal to a potential of a single power source can be achieved.
Public/Granted literature
- US20220366958A1 MEMORY CIRCUIT USING OXIDE SEMICONDUCTOR Public/Granted day:2022-11-17
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