Invention Grant
- Patent Title: Accessing data using error correction operation(s) to reduce latency at a memory sub-system
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Application No.: US17877637Application Date: 2022-07-29
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Publication No.: US12007838B2Publication Date: 2024-06-11
- Inventor: Vamsi Pavan Rayaprolu , Dung Viet Nguyen , Zixiang Loh , Sampath K Ratnam , Patrick R. Khayat , Thomas Herbert Lentz
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: LOWENSTEIN SANDLER LLP
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/10
Abstract:
A request to access data programmed to a memory sub-system is received. A determination is made of whether memory cells of the memory sub-system that store the programmed data satisfy one or more cell degradation criteria. In response to a determination that the memory cells satisfy the one or more cell degradation criteria, an error correction operation to access the data is performed in accordance with the request.
Public/Granted literature
- US20240036973A1 ACCESSING DATA USING ERROR CORRECTION OPERATION(S) TO REDUCE LATENCY AT A MEMORY SUB-SYSTEM Public/Granted day:2024-02-01
Information query
