A graphics processor having a command processor and a geometry engine and connected to a memory and another graphics processor includes a bus fabric that delivers and receives data to and from the memory connected thereto, and a first interconnect that is connected to the command processor and the geometry engine and that delivers and receives data to and from a command processor and a geometry engine of the other graphics processor. Via a second interconnect, the bus fabric delivers and receives data to and from a bus fabric of the other graphics processor, and is accessibly connected to a memory connected to the other graphics processor.