Adaptive semi-circle select gate bias
Abstract:
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and arranged in strings. Each of the strings has a drain-side select gate transistor on a drain-side connected to one of a plurality of bit lines. A control means is coupled to the word lines and the plurality of bit lines and the drain-side select gate transistors. The control means determines a unique select gate voltage for each of a plurality of groupings of the memory cells that is individually adapted for each of the plurality of groupings. The control means then applies the unique select gate voltage to the drain-side select gate transistor of selected ones of the strings of each of the plurality of groupings of the memory cells to turn on the drain-side select gate transistor of the selected ones of the strings during a memory operation.
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