Invention Grant
- Patent Title: Switch capacitance cancellation circuit
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Application No.: US17351128Application Date: 2021-06-17
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Publication No.: US12028060B2Publication Date: 2024-07-02
- Inventor: David Kovac , Joseph Golat
- Applicant: Murata Manufacturing Co., Ltd.
- Applicant Address: JP Nagaokakyo
- Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee: Murata Manufacturing Co., Ltd.
- Current Assignee Address: JP Nagaokakyo
- Agency: Steinfl + Bruno LLP
- Main IPC: H03K17/687
- IPC: H03K17/687 ; H01L23/66 ; H03K19/003

Abstract:
Methods and devices used to cancel non-linear capacitances in high power radio frequency (RF) switches manufactured in bulk complementary metal-oxide-semiconductor (CMOS) processes are disclosed. The methods and devices are also applicable to stacked switches and RF switches fabricated in silicon-on-insulator (SOI) technology.
Public/Granted literature
- US20220407512A1 SWITCH CAPACITANCE CANCELLATION CIRCUIT Public/Granted day:2022-12-22
Information query
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