- 专利标题: Memory circuit arrangement for accurate and secure read
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申请号: US18063041申请日: 2022-12-07
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公开(公告)号: US12033715B2公开(公告)日: 2024-07-09
- 发明人: Vikas Rana , Arpit Vijayvergia
- 申请人: STMicroelectronics International N.V.
- 申请人地址: CH Geneva
- 专利权人: STMicroelectronics International N.V.
- 当前专利权人: STMicroelectronics International N.V.
- 当前专利权人地址: CH Geneva
- 代理机构: Seed IP Law Group LLP
- 主分类号: G11C7/00
- IPC分类号: G11C7/00 ; G11C7/06 ; H03K19/20
摘要:
The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.
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