Invention Grant
- Patent Title: Multi-layer high-k gate dielectric structure
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Application No.: US17884442Application Date: 2022-08-09
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Publication No.: US12041760B2Publication Date: 2024-07-16
- Inventor: Chih-Yu Hsu , Jian-Hao Chen , Chia-Wei Chen , Shan-Mei Liao , Hui-Chi Chen , Yu-Chia Liang , Shih-Hao Lin , Kuei-Lun Lin , Kuo-Feng Yu , Feng-Cheng Yang , Yen-Ming Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- The original application number of the division: US17036418 2020.09.29
- Main IPC: H01L27/11
- IPC: H01L27/11 ; H10B10/00

Abstract:
A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.
Public/Granted literature
- US20220384454A1 Multi-Layer High-K Gate Dielectric Structure Public/Granted day:2022-12-01
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