公开(公告)号：US12266655B2

公开(公告)日：2025-04-01

申请号：US17657833

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Bo-Yu Lai ,  Chien-Wei Lee ,  Hsueh-Chang Sung ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.

公开(公告)号：US12218138B2

公开(公告)日：2025-02-04

申请号：US18510370

申请日：2023-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Yu Lai ,  Kai-Hsuan Lee ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311

Abstract: A semiconductor device includes source/drain regions, a gate structure, a first gate spacer, and a dielectric material. The source/drain regions are over a substrate. The gate structure is laterally between the source/drain regions. The first gate spacer is on a first sidewall of the gate structure, and spaced apart from a first one of the source/drain regions at least in part by a void region. The dielectric material is between the first one of the source/drain regions and the void region. The dielectric material has a gradient ratio of a first chemical element to a second chemical element.

公开(公告)号：US20240389334A1

公开(公告)日：2024-11-21

申请号：US18785757

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H10B51/20 ,  G11C11/22 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H10B43/20 ,  H10B43/27 ,  H10B51/10 ,  H10B51/30

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

公开(公告)号：US20240381608A1

公开(公告)日：2024-11-14

申请号：US18781832

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Hsu ,  Jian-Hao Chen ,  Chia-Wei Chen ,  Shan-Mei Liao ,  Hui-Chi Chen ,  Yu-Chia Liang ,  Shih-Hao Lin ,  Kuei-Lun Lin ,  Kuo-Feng Yu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H10B10/00

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

公开(公告)号：US12136673B2

公开(公告)日：2024-11-05

申请号：US18447855

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ta Yu ,  Yen-Chieh Huang ,  Wei-Yuan Lu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/165

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.

公开(公告)号：US20240284679A1

公开(公告)日：2024-08-22

申请号：US18631842

申请日：2024-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Chung-Te Lin

IPC: H10B51/20 ,  G11C5/06 ,  G11C11/22 ,  H01L21/822 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B51/20 ,  G11C5/06 ,  G11C11/223 ,  H01L21/8221 ,  H01L29/6684 ,  H01L29/78391

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.

公开(公告)号：US12068204B2

公开(公告)日：2024-08-20

申请号：US18359254

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

公开(公告)号：US20240251539A1

公开(公告)日：2024-07-25

申请号：US18587506

申请日：2024-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B10/12 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31053 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H10B10/18

Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

公开(公告)号：US12027412B2

公开(公告)日：2024-07-02

申请号：US17814626

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L21/762 ,  G11C7/18 ,  H10B51/20 ,  H10B99/00

CPC classification number: H01L21/76237 ,  G11C7/18 ,  H10B51/20 ,  H10B99/00

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric material.

公开(公告)号：US12009263B2

公开(公告)日：2024-06-11

申请号：US17350177

申请日：2021-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen ,  Sai-Hooi Yeong

IPC: H01L21/3105 ,  H01L21/285 ,  H01L21/764 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/28518 ,  H01L21/31055 ,  H01L21/764 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/785

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed adjacent to a metal gate structure (MG), an S/D contact disposed over the S/D feature, and a dielectric layer disposed over the S/D contact, where the S/D feature and the S/D contact are separated from the MG by a first air gap, where the dielectric layer partially fills the first air gap, and where a bottom portion of a bottom surface of the S/D contact is separated from a top portion of the S/D feature by a second air gap that is connected to the first air gap.