公开(公告)号：US20230101134A1

公开(公告)日：2023-03-30

申请号：US17986451

申请日：2022-11-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Hsin Yang ,  Yen-Ming Chen ,  Feng-Cheng Yang ,  Tsung-Lin Lee ,  Wei-Yang Lee ,  Dian-Hau Chen

IPC分类号： H01L29/49 ,  G06F30/392 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

摘要： A semiconductor device includes a substrate. A gate structure is disposed over the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction that is different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.

公开(公告)号：US11616142B2

公开(公告)日：2023-03-28

申请号：US17542810

申请日：2021-12-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Ta Yu ,  Yen-Chieh Huang ,  Wei-Yuan Lu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165

摘要： A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.

公开(公告)号：US11574929B2

公开(公告)日：2023-02-07

申请号：US17113249

申请日：2020-12-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sheng-Chen Wang ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Han-Jong Chia

IPC分类号： H01L27/11597 ,  H01L27/1159 ,  H01L27/11587 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/786

摘要： A 3D memory array has data storage structures provided at least in part by one or more vertical films that do not extend between vertically adjacent memory cells. The 3D memory array includes conductive strips and dielectric strips, alternately stacked over a substrate. The conductive strips may be laterally indented from the dielectric strips to form recesses. A data storage film may be disposed within these recesses. Any portion of the data storage film deposited outside the recesses may have been effectively removed, whereby the data storage film is essentially discontinuous from tier to tier within the 3D memory array. The data storage film within each tier may have upper and lower boundaries that are the same as those of a corresponding conductive strip. The data storage film may also be made discontinuous between horizontally adjacent memory cells.

公开(公告)号：US20220384454A1

公开(公告)日：2022-12-01

申请号：US17884442

申请日：2022-08-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Yu Hsu ,  Jian-Hao Chen ,  Chia-Wei Chen ,  Shan-Mei Liao ,  Hui-Chi Chen ,  Yu-Chia Liang ,  Shih-Hao Lin ,  Kuei-Lun Lin ,  Kuo-Feng Yu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC分类号： H01L27/11

摘要： A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

公开(公告)号：US20220320119A1

公开(公告)日：2022-10-06

申请号：US17345499

申请日：2021-06-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Wei Jiang ,  Sheng-Chih Lai ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC分类号： H01L27/1159 ,  H01L27/11587

摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a stacked structure disposed on the substrate. The stacked structure includes multiple alternately stacked insulating layers and gate members. A core structure is disposed in the stacked structure. The core structure includes a memory layer, a channel member, a contact member, and a liner member. The channel member is disposed on the memory layer. The contact member is disposed on the channel member. The liner member surrounds a portion of the core structure. The present disclosure also provides a method for fabricating the semiconductor structure.

公开(公告)号：US20220302299A1

公开(公告)日：2022-09-22

申请号：US17833356

申请日：2022-06-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-An Lin ,  Wei-Yuan Lu ,  Feng-Cheng Yang ,  Tzu-Ching Lin ,  Li-Li Su

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  A61B5/15 ,  G01N1/14 ,  G01N33/49

摘要： The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.

公开(公告)号：US11423966B2

公开(公告)日：2022-08-23

申请号：US17081380

申请日：2020-10-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC分类号： G11C8/14 ,  H01L21/822 ,  H01L21/8239 ,  H01L27/105 ,  H01L27/11597

摘要： Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line extending from a first edge of the memory array in a first direction, the first word line having a length less than a length of a second edge of the memory array perpendicular to the first edge of the memory array; a second word line extending from a third edge of the memory array opposite the first edge of the memory array, the second word line extending in the first direction, the second word line having a length less than the length of the second edge of the memory array; a memory film contacting the first word line; and an OS layer contacting a first source line and a first bit line, the memory film being disposed between the OS layer and the first word line.

公开(公告)号：US11355641B2

公开(公告)日：2022-06-07

申请号：US17201147

申请日：2021-03-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-An Lin ,  Wei-Yuan Lu ,  Feng-Cheng Yang ,  Tzu-Ching Lin ,  Li-Li Su

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  A61B5/15 ,  G01N1/14 ,  G01N33/49 ,  H01L29/04

摘要： The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.

公开(公告)号：US20220020771A1

公开(公告)日：2022-01-20

申请号：US17018232

申请日：2020-09-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Han-Jong Chia ,  Chung-Te Lin

IPC分类号： H01L27/11597 ,  H01L27/1159 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/768

摘要： In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

公开(公告)号：US20210376077A1

公开(公告)日：2021-12-02

申请号：US17397728

申请日：2021-08-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Feng-Ching Chu ,  Wei-Yang Lee ,  Yen-Ming Chen ,  Feng-Cheng Yang

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L29/78 ,  H01L21/306

摘要： Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.