发明授权
- 专利标题: Analog-to-digital conversion circuit and method having speed-up comparison mechanism
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申请号: US17946072申请日: 2022-09-16
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公开(公告)号: US12052027B2公开(公告)日: 2024-07-30
- 发明人: Wei-Cian Hong
- 申请人: REALTEK SEMICONDUCTOR CORPORATION
- 申请人地址: TW Hsinchu
- 专利权人: REALTEK SEMICONDUCTOR CORPORATION
- 当前专利权人: REALTEK SEMICONDUCTOR CORPORATION
- 当前专利权人地址: TW Hsinchu
- 代理机构: WPAT, P.C
- 优先权: TW 0146083 2021.12.09
- 主分类号: H03M1/34
- IPC分类号: H03M1/34 ; H03M1/46 ; H03M1/80 ; H03M1/82
摘要:
The present invention discloses an analog-to-digital conversion circuit having speed-up comparison mechanism. Each of a positive and a negative capacitor arrays receives a positive and a negative input voltages to generate a positive and a negative output voltages. A first comparator performs comparison thereon to generate a first comparison result and a second comparator performs comparison according to a reference voltage to generate a second comparison result. A control circuit switches a capacitor enabling combination of the capacitor arrays according to the first comparison result and outputs a digital code as a digital output signal when the positive and the negative output voltages equal. The control circuit operates in a speed-up switching mode when a difference between the positive and the negative output voltages is outside of a predetermined range defined by the reference voltage and operates in a normal switching mode when the difference is within the predetermined range.
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