Analog-to-digital conversion circuit and method having speed-up comparison mechanism
摘要:
The present invention discloses an analog-to-digital conversion circuit having speed-up comparison mechanism. Each of a positive and a negative capacitor arrays receives a positive and a negative input voltages to generate a positive and a negative output voltages. A first comparator performs comparison thereon to generate a first comparison result and a second comparator performs comparison according to a reference voltage to generate a second comparison result. A control circuit switches a capacitor enabling combination of the capacitor arrays according to the first comparison result and outputs a digital code as a digital output signal when the positive and the negative output voltages equal. The control circuit operates in a speed-up switching mode when a difference between the positive and the negative output voltages is outside of a predetermined range defined by the reference voltage and operates in a normal switching mode when the difference is within the predetermined range.
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