A circuit receives an input clock pulse signal characterized by a first frequency and a first pulse width, and produces an output pulse signal characterized by a second frequency that is half of the first frequency and a second pulse width that is equal to the first pulse width. The circuit also includes a first D-flipflop, a first inverter, a first Schmitt trigger, and a first AND gate. The first D-flipflop includes a clock input terminal for receiving the input clock pulse signal and an output terminal for producing a first data output. The first inverter couples the output terminal and a data input terminal of the first D-flipflop. A first Schmitt trigger receives the input clock pulse signal and provides a first delayed input clock signal. The first AND gate receives the first data output and the first delayed input clock signal, and provides the output pulse signal.