Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.