公开(公告)号：US12062574B2

公开(公告)日：2024-08-13

申请号：US17389779

申请日：2021-07-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Zhong-Xiang He ,  Richard J. Rassel ,  Alvin J. Joseph ,  Ramsey M. Hazbun ,  Jeonghyun Hwang ,  Mark D. Levy

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/76898 ,  H01L21/823475 ,  H01L23/481 ,  H01L29/66462 ,  H01L29/7786

Abstract: Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.

公开(公告)号：US20230034728A1

公开(公告)日：2023-02-02

申请号：US17389779

申请日：2021-07-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Zhong-Xiang He ,  Richard J. Rassel ,  Alvin J. Joseph ,  Ramsey M. Hazbun ,  Jeonghyun Hwang ,  Mark D. Levy

IPC: H01L21/768 ,  H01L23/48 ,  H01L29/778 ,  H01L29/66 ,  H01L21/8234

Abstract: Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.

公开(公告)号：US20240063219A1

公开(公告)日：2024-02-22

申请号：US17819980

申请日：2022-08-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Jerry Joseph James ,  Steven J. Bentley ,  Francois Hebert ,  Richard J. Rassel

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L27/0883 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/401 ,  H01L29/402 ,  H01L29/0607

Abstract: A structure for an III-V integrated circuit includes an integrated depletion and enhancement mode gallium nitride high electron mobility transistors (HEMTs). The structure includes a first, depletion mode HEMT having a first source, a first drain and a first fieldplate gate between the first source and the first drain, and a second, enhancement mode HEMT having a second source and a second drain. The second HEMT also includes a gallium nitride (GaN) gate and a second fieldplate gate between the second source and the second drain. The second fieldplate gate of the second HEMT may be closer to the second drain than the GaN gate. The structure provides a reliable, low leakage, high voltage depletion mode HEMT (e.g., with operating voltages of greater than 100V, but with a pinch-off voltage of less than 6 Volts) integrated with a gallium nitride (GaN) gate-based enhancement mode HEMT.