Invention Grant
- Patent Title: Semiconductor memory device and test method for the same
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Application No.: US17900228Application Date: 2022-08-31
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Publication No.: US12073900B2Publication Date: 2024-08-27
- Inventor: Haruyuki Okuda
- Applicant: RENESAS ELECTRONICS CORPORATION
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Rimon P.C.
- Priority: JP 2021165848 2021.10.08
- Main IPC: G11C29/12
- IPC: G11C29/12 ; G11C11/418

Abstract:
A semiconductor device includes memory cells, word lines, a row address decoder, word line drivers, a first switch transistor, and second switch transistors. The switch transistor is provided between the word line drivers and a power supply potential terminal. Each second switch transistor is provided between each word line and a reference potential terminal. The row address decoder activates all of decode signals corresponding to the memory cells to which a burn-in test is performed collectively. The first switch transistor has a lower driving capability than a total driving capability of two P-channel MOS transistors included in inverters of two word line drivers. Each second switch transistor has a lower driving capability than a driving capability of an N-channel MOS transistor included in the inverter of each word line driver.
Public/Granted literature
- US20230115776A1 SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD FOR THE SAME Public/Granted day:2023-04-13
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