Invention Grant
- Patent Title: Balancing performance between interface ports in a memory sub-system
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Application No.: US17900120Application Date: 2022-08-31
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Publication No.: US12086412B2Publication Date: 2024-09-10
- Inventor: Raja V. S. Halaharivi , Prateek Sharma
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
A system includes a memory device, a first interface port and a second interface port operatively coupled with the memory device, and a processing device, operatively coupled with the memory device, to perform operations including: detecting a triggering event associated with the first interface port; responsive to detecting the triggering event, sending an interrupt message to a firmware component of the memory device; receiving, from the firmware component, a configuration setting based on the interrupt message; and allocating, by the processing device, one or more resources to the first interface port according to the configuration setting.
Public/Granted literature
- US20240069732A1 BALANCING PERFORMANCE BETWEEN INTERFACE PORTS IN A MEMORY SUB-SYSTEM Public/Granted day:2024-02-29
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