公开(公告)号：US12086412B2

公开(公告)日：2024-09-10

申请号：US17900120

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Raja V. S. Halaharivi ,  Prateek Sharma

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0679

Abstract: A system includes a memory device, a first interface port and a second interface port operatively coupled with the memory device, and a processing device, operatively coupled with the memory device, to perform operations including: detecting a triggering event associated with the first interface port; responsive to detecting the triggering event, sending an interrupt message to a firmware component of the memory device; receiving, from the firmware component, a configuration setting based on the interrupt message; and allocating, by the processing device, one or more resources to the first interface port according to the configuration setting.

公开(公告)号：US20210200568A1

公开(公告)日：2021-07-01

申请号：US16868643

申请日：2020-05-07

Applicant: Micron Technology, Inc.

Inventor： Prateek Sharma ,  Bridget L. Mallak ,  Kevin R. Duncan

IPC: G06F9/455 ,  G06F9/48 ,  G06F9/445 ,  G06F9/38 ,  G06F13/16 ,  G06F11/30

Abstract: A processing device of a memory sub-system can receive a plurality of commands from a plurality of virtual machines via a host interface and associate each of the plurality of commands with a respective function that represents a respective virtual machine from which each of the plurality of commands was received. The controller of the memory sub-system can also setup a respective definition of a respective quality of service for each respective function regarding consumption of resources of the memory device, wherein the controller comprises arbitration circuitry to handle each of the plurality of commands on a per function basis according to the definition.

公开(公告)号：US20240069807A1

公开(公告)日：2024-02-29

申请号：US17900122

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Raja V.S. Halaharivi ,  Prateek Sharma ,  Venkat R. Gaddam

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving, from a host system, a memory access command; executing the memory access command; identifying a characteristic associated with the memory access command; identifying a threshold period of time corresponding to the characteristic associated with the memory access command; determining that a period of time associated with the memory access command satisfies the threshold period of time; and responsive to determining that the period of time associated with the memory access command satisfies the threshold period of time, notifying the host system of completion of execution of the memory access command.

公开(公告)号：US20240069732A1

公开(公告)日：2024-02-29

申请号：US17900120

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Raja V.S. Halaharivi ,  Prateek Sharma

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0679

Abstract: A system includes a memory device, a first interface port and a second interface port operatively coupled with the memory device, and a processing device, operatively coupled with the memory device, to perform operations including: detecting a triggering event associated with the first interface port; responsive to detecting the triggering event, sending an interrupt message to a firmware component of the memory device; receiving, from the firmware component, a configuration setting based on the interrupt message; and allocating, by the processing device, one or more resources to the first interface port according to the configuration setting.

公开(公告)号：US11321238B2

公开(公告)日：2022-05-03

申请号：US16990941

申请日：2020-08-11

Applicant: Micron Technology, Inc.

Inventor： Prateek Sharma

IPC: G06F12/1009 ,  G06F12/1045 ,  G06F9/54 ,  G06F9/455

Abstract: A processing device of a memory sub-system can receive a first address from a host and can provide the first address to a memory management unit (MMU) for translation. The processing device can also receive a second address from the MMU wherein the second address is translated from the first address. The processing device can further access the memory device utilizing the second address.

公开(公告)号：US12298916B2

公开(公告)日：2025-05-13

申请号：US18517370

申请日：2023-11-22

Applicant: Micron Technology, Inc.

Inventor： Prateek Sharma ,  Raja V. S. Halaharivi ,  Sumangal Chakrabarty ,  Venkat R. Gaddam

IPC: G06F12/123 ,  G06F12/0882

Abstract: A device includes an address translation circuit of host interface circuitry to handle address translation requests to a host system from a host queue interface circuit. The address translation circuit includes cache to store address translations associated with the address translation requests. The host queue interface circuit, coupled to the address translation circuit, is to: pause command fetch arbitration on a submission queue of the host system that is targeted by an address translation request that missed at the cache; trigger a page request interface (PRI) handler to send a page miss request to a translation agent (TA) of the host, the page miss request including a virtual address of the address translation request; receive a restart message from the PRI handler upon the PRI handler receiving a page miss response from the TA; and restart command arbitration on the submission queue that was paused responsive to the restart message.

公开(公告)号：US20240160553A1

公开(公告)日：2024-05-16

申请号：US18388610

申请日：2023-11-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Raja V.S. Halaharivi ,  Prateek Sharma ,  Horia C. Simionescu

IPC: G06F11/34

CPC classification number: G06F11/3428

Abstract: A memory system includes a memory device and a processing device coupled to the memory device, the processing device is to present a plurality of physical or virtual functions (PFs/VFs) to a host computing system; set, for each of the plurality of PFs/VFs, a value of a credit counter to an initial value associated with a Quality of Service (QoS) parameter of a respective PF/VF; responsive to fetching an original command received from the host computing system associated with a specified PF/VF, decrement the value of the credit counter associated with the specified PF/VF; responsive to receiving a reintroduced command associated with the specified PF/VF after the original command, increment the value of the credit counter; determine whether the value of the credit counter is not higher than a threshold value; and responsive to determining that the value of the credit counter is higher than the threshold value, continue fetching a subsequent command associated with the specified PF/VF.

公开(公告)号：US11734191B2

公开(公告)日：2023-08-22

申请号：US17711581

申请日：2022-04-01

Applicant: Micron Technology, Inc.

Inventor： Prateek Sharma

IPC: G06F12/1009 ,  G06F12/1045 ,  G06F9/54 ,  G06F9/455

CPC classification number: G06F12/1009 ,  G06F9/45558 ,  G06F9/546 ,  G06F12/1063 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/657

Abstract: A processing device of a memory sub-system can receive a first address from a host and can provide the first address to a memory management unit (MMU) for translation. The processing device can also receive a second address from the MMU wherein the second address is translated from the first address. The processing device can further access the memory device utilizing the second address.

公开(公告)号：US20240411704A1

公开(公告)日：2024-12-12

申请号：US18675476

申请日：2024-05-28

Applicant: Micron Technology, Inc.

Inventor： Raja V.S. Halaharivi ,  Prateek Sharma ,  Sumangal Chakrabarty ,  Venkat R. Gaddam

IPC: G06F12/1045

Abstract: A method, performed by pointer fetch circuitry, includes buffering, in a pointer buffer of host interface circuitry, pointers associated with chop commands of a logical block address read command residing in a submission queue of a host system. The method includes sending address translation requests to an address translation circuit for respective translation units of respective chop commands, each translation unit includes a subset of the pointers. The method includes detecting an address translation request miss at a cache of the address translation circuit for a translation unit of a chop command. The method includes sending a translation miss message to a page request interface (PRI) handler. The translation miss message contains a virtual address of the translation unit and a restart point for the chop command, the translation miss message to trigger the PRI handler to send a page miss request to a translation agent of the host system.

公开(公告)号：US20240411700A1

公开(公告)日：2024-12-12

申请号：US18675486

申请日：2024-05-28

Applicant: Micron Technology, Inc.

Inventor： Raja V.S. Halaharivi ,  Prateek Sharma ,  Sumangal Chakrabarty ,  Venkat R. Gaddam

IPC: G06F12/10 ,  G06F12/0802

Abstract: A method includes buffering, in a descriptor queue, descriptors associated with translation units of an LBA-based, direct memory access (DMA) read command of a host system, each descriptor to be linked with a pointer including a physical destination for data associated with a respective translation unit. The method includes sending address translation requests to an address translation circuit for the pointers of respective translation units and detecting an address translation request miss at a cache of the address translation circuit for a first pointer of a first translation unit linked to a first descriptor of the plurality of descriptors. The method includes causing a translation miss message to be sent to a page request interface (PRI) handler, the translation miss message containing a virtual address of the first pointer and to trigger the PRI handler to send a page miss request to a translation agent of the host system.