- 专利标题: High throughput parallel architecture for recursive sinusoid synthesizer
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申请号: US18134737申请日: 2023-04-14
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公开(公告)号: US12086568B2公开(公告)日: 2024-09-10
- 发明人: Ankur Bal , Rupesh Singh
- 申请人: STMicroelectronics International N.V.
- 申请人地址: CH Geneva
- 专利权人: STMicroelectronics International N.V.
- 当前专利权人: STMicroelectronics International N.V.
- 当前专利权人地址: CH Geneva
- 代理机构: Crowe & Dunlevy LLC
- 分案原申请号: US16988912 2020.08.10
- 主分类号: G06F7/544
- IPC分类号: G06F7/544 ; G06F7/548 ; H03K3/037 ; H03K5/01 ; H03K5/00
摘要:
A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.
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