Invention Grant
- Patent Title: Non-conductive etch stop structures for memory applications with large contact height differential
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Application No.: US17441217Application Date: 2019-05-09
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Publication No.: US12087693B2Publication Date: 2024-09-10
- Inventor: Daniel R. Lamborn , Chuan Sun , Qi Zhou
- Applicant: Intel NDTM US LLC
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- International Application: PCT/CN2019/086118 2019.05.09
- International Announcement: WO2020/223945A 2020.11.12
- Date entered country: 2021-09-20
- Main IPC: H10B43/50
- IPC: H10B43/50 ; H01L21/768 ; H01L23/528 ; H01L23/535 ; H10B41/50 ; H10B43/27

Abstract:
Etch stops are disclosed for integrated circuit applications that have a set contacts of varying height, wherein there is a large height differential between the shortest and tallest contacts. In one example, an etch stop is provisioned over a 3D NAND memory staircase structure. The structure is then planarized with an insulator material that can be selectively etched with respect to the etch stop. Contact holes that land on corresponding wordlines of the staircase are etched. Due to the nature of the staircase, the holes vary in depth depending on which step of the staircase they land. The etch stop under the shallowest hole remains intact while the deepest hole is etched to completion. Once all holes have landed on the etch stop, a further etch selective to the insulator material is carried out to punch through the etch stop and expose underlying wordlines. Contacts are deposited into the holes.
Public/Granted literature
- US20220148971A1 NON-CONDUCTIVE ETCH STOP STRUCTURES FOR MEMORY APPLICATIONS WITH LARGE CONTACT HEIGHT DIFFERENTIAL Public/Granted day:2022-05-12
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