Invention Grant
- Patent Title: Reducing back powering in I/O circuits
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Application No.: US17489535Application Date: 2021-09-29
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Publication No.: US12087774B2Publication Date: 2024-09-10
- Inventor: Madhuresh Sinha , Subramanian Jagdish Narayan
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Valerie M. Davis; Frank D. Cimino
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L27/02

Abstract:
In examples, an input/output (I/O) circuit comprises an input, an output, and a first transistor having a first control terminal, a first current terminal and a second current terminal, the first current terminal coupled to the input. The circuit also includes a second transistor having a second control terminal, a third current terminal and a fourth current terminal, the third current terminal coupled to ground and the fourth current terminal coupled to the second current terminal. The circuit further includes a third transistor having a third control terminal, a fifth current terminal and a sixth current terminal, the third transistor coupled between the input and the output and the third control terminal coupled to the second current terminal.
Public/Granted literature
- US20230098179A1 REDUCING BACK POWERING IN I/O CIRCUITS Public/Granted day:2023-03-30
Information query
IPC分类: