公开(公告)号：US12087774B2

公开(公告)日：2024-09-10

申请号：US17489535

申请日：2021-09-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Madhuresh Sinha ,  Subramanian Jagdish Narayan

IPC: H01L27/092 ,  H01L27/02

CPC classification number: H01L27/0922 ,  H01L27/0207

Abstract: In examples, an input/output (I/O) circuit comprises an input, an output, and a first transistor having a first control terminal, a first current terminal and a second current terminal, the first current terminal coupled to the input. The circuit also includes a second transistor having a second control terminal, a third current terminal and a fourth current terminal, the third current terminal coupled to ground and the fourth current terminal coupled to the second current terminal. The circuit further includes a third transistor having a third control terminal, a fifth current terminal and a sixth current terminal, the third transistor coupled between the input and the output and the third control terminal coupled to the second current terminal.

公开(公告)号：US09602084B2

公开(公告)日：2017-03-21

申请号：US14966616

申请日：2015-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subramanian Jagdish Narayan ,  Dipankar Mandal ,  Janakiraman Seetharaman ,  Kiran Godbole

IPC: G01R23/02 ,  H03K3/037 ,  G01R19/165

CPC classification number: H03K3/037 ,  G01R19/1659 ,  H03K3/0231

Abstract: Frequency detector and oscillator circuits are disclosed. Example frequency detector and oscillator circuits disclosed herein include a current approximation circuit coupled to an external clock operating at a target frequency. In some examples, the current approximation circuit is configured to determine a magnitude of a first current to charge a capacitor to reach a reference voltage during a first set of clock cycles generated by the external clock. In some examples, the current approximation circuit is further configured to generate an output current based on the magnitude of the first current and to use the output current to produce a comparator output. In some examples, the frequency detector and oscillator circuits further include a latching circuit coupled to receive the comparator output from the current approximation circuit. In some such examples, the latching circuit is configured to generate oscillating signals at the target frequency based on the comparator output.

公开(公告)号：US20150188561A1

公开(公告)日：2015-07-02

申请号：US14255269

申请日：2014-04-17

Applicant: Texas Instruments Incorporated

Inventor： Subramanian Jagdish Narayan ,  Anand Kannan

IPC: H03M1/38 ,  H03M1/66 ,  H03M1/06

CPC classification number: H03M1/144 ,  H03M1/0604 ,  H03M1/0695 ,  H03M1/468

Abstract: A successive approximation register analog to digital converter (SAR ADC) is disclosed. The SAR ADC receives an input voltage and a plurality of reference voltages. The SAR ADC includes a charge sharing DAC. The charge sharing DAC includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A coarse ADC (analog to digital converter) receives the input voltage and generates a coarse output. A predefined offset is added to a residue of the coarse ADC. A successive approximation register (SAR) state machine is coupled to the coarse ADC and the zero crossing detector and, generates a plurality of control signals. The plurality of control signals operates the charge sharing DAC in a sampling mode, an error-correction mode and a conversion mode.

Abstract translation: 公开了逐次逼近寄存器模数转换器（SAR ADC）。 SAR ADC接收输入电压和多个参考电压。 SAR ADC包含一个电荷共享DAC。 电荷共享DAC包括一个MSB（最高有效位）电容器阵列和一个LSB​​（最低有效位）电容器阵列。 零交叉检测器耦合到电荷共享DAC。 过零检测器产生数字输出。 粗略的ADC（模数转换器）接收输入电压并产生粗略的输出。 将预定义的偏移量添加到粗略ADC的残差。 逐次逼近寄存器（SAR）状态机耦合到粗略ADC和过零检测器，并产生多个控制信号。 多个控制信号以采样模式，纠错模式和转换模式操作电荷共享DAC。

公开(公告)号：US10763886B1

公开(公告)日：2020-09-01

申请号：US16545058

申请日：2019-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subramanian Jagdish Narayan ,  Chandana Krishna

IPC: H03M3/00 ,  H03M1/68 ,  H03M1/16 ,  H03M1/44

Abstract: A multi-stage analog-to-digital converter includes a signal input terminal, a first stage analog-to-digital converter, a digital-to-analog converter; a second stage analog-to-digital converter, and dither circuitry. The first stage analog-to-digital converter includes an input coupled to the signal input terminal. The digital-to-analog converter includes an input coupled to an output of the first stage analog-to-digital converter, and an input coupled to the signal input terminal. The second stage analog-to-digital converter includes a first input coupled to an output of the digital-to-analog converter. The dither circuitry is coupled to a second input of the second stage analog-to-digital converter, and is configured to provide a dither signal to the second stage analog-to-digital converter during selection of fewer than all bits of a digital value of a residue signal received from the digital-to-analog converter.

公开(公告)号：US20160308516A1

公开(公告)日：2016-10-20

申请号：US14966616

申请日：2015-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subramanian Jagdish Narayan ,  Dipankar Mandal ,  Janakiraman Seetharaman ,  Kiran Godbole

IPC: H03K3/037 ,  G01R19/165

CPC classification number: H03K3/037 ,  G01R19/1659 ,  H03K3/0231

Abstract: Frequency detector and oscillator circuits are disclosed. Example frequency detector and oscillator circuits disclosed herein include a current approximation circuit coupled to an external clock operating at a target frequency. In some examples, the current approximation circuit is configured to determine a magnitude of a first current to charge a capacitor to reach a reference voltage during a first set of clock cycles generated by the external clock. In some examples, the current approximation circuit is further configured to generate an output current based on the magnitude of the first current and to use the output current to produce a comparator output. In some examples, the frequency detector and oscillator circuits further include a latching circuit coupled to receive the comparator output from the current approximation circuit. In some such examples, the latching circuit is configured to generate oscillating signals at the target frequency based on the comparator output.

Abstract translation: 公开了频率检测器和振荡器电路。 本文公开的示例性频率检测器和振荡器电路包括耦合到以目标频率工作的外部时钟的电流近似电路。 在一些示例中，电流近似电路被配置为在由外部时钟产生的第一组时钟周期期间确定用于对电容器充电以达到参考电压的第一电流的幅度。 在一些示例中，电流近似电路还被配置为基于第一电流的幅度产生输出电流并且使用输出电流来产生比较器输出。 在一些示例中，频率检测器和振荡器电路还包括耦合以从电流近似电路接收比较器输出的锁存电路。 在一些这样的示例中，锁存电路被配置为基于比较器输出以目标频率产生振荡信号。

公开(公告)号：US09148166B2

公开(公告)日：2015-09-29

申请号：US14255269

申请日：2014-04-17

Applicant: Texas Instruments Incorporated

Inventor： Subramanian Jagdish Narayan ,  Anand Kannan

IPC: H03M1/06 ,  H03M1/38 ,  H03M1/66

CPC classification number: H03M1/144 ,  H03M1/0604 ,  H03M1/0695 ,  H03M1/468

Abstract: A successive approximation register analog to digital converter (SAR ADC) receives an input voltage and a plurality of reference voltages. The SAR ADC includes a charge sharing DAC. The charge sharing DAC includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A coarse ADC (analog to digital converter) receives the input voltage and generates a coarse output. A predefined offset is added to a residue of the coarse ADC. A successive approximation register (SAR) state machine is coupled to the coarse ADC and the zero crossing detector and, generates a plurality of control signals. The plurality of control signals operates the charge sharing DAC in a sampling mode, an error-correction mode and a conversion mode.

Abstract translation: 逐次逼近寄存器模数转换器（SAR ADC）接收输入电压和多个参考电压。 SAR ADC包含一个电荷共享DAC。 电荷共享DAC包括一个MSB（最高有效位）电容器阵列和一个LSB​​（最低有效位）电容器阵列。 零交叉检测器耦合到电荷共享DAC。 过零检测器产生数字输出。 粗略的ADC（模数转换器）接收输入电压并产生粗略的输出。 将预定义的偏移量添加到粗略ADC的残差。 逐次逼近寄存器（SAR）状态机耦合到粗略ADC和过零检测器，并产生多个控制信号。 多个控制信号以采样模式，纠错模式和转换模式操作电荷共享DAC。