Invention Grant
- Patent Title: Stochastic optimization of surface cacheability in parallel processing units
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Application No.: US17557475Application Date: 2021-12-21
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Publication No.: US12117939B2Publication Date: 2024-10-15
- Inventor: Saurabh Sharma , Jeremy Lukacs , Hashem Hashemi , Gianpaolo Tommasi , Christopher J. Brennan
- Applicant: ADVANCED MICRO DEVICES, INC.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/0893

Abstract:
A processing system selectively allocates storage at a local cache of a parallel processing unit for cache lines of a repeating pattern of data that exceeds the storage capacity of the cache. The processing system identifies repeating patterns of data having cache lines that have a reuse distance that exceeds the storage capacity of the cache. A cache controller allocates storage for only a subset of cache lines of the repeating pattern of data at the cache and excludes the remainder of cache lines of the repeating pattern of data from the cache. By restricting the cache to store only a subset of cache lines of the repeating pattern of data, the cache controller increases the hit rate at the cache for the subset of cache lines.
Public/Granted literature
- US20230195639A1 STOCHASTIC OPTIMIZATION OF SURFACE CACHEABILITY IN PARALLEL PROCESSING UNITS Public/Granted day:2023-06-22
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