Invention Grant
- Patent Title: Hardware translation request retry mechanism
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Application No.: US17529499Application Date: 2021-11-18
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Publication No.: US12124381B2Publication Date: 2024-10-22
- Inventor: Edwin Pang
- Applicant: ATI TECHNOLOGIES ULC
- Applicant Address: CA Markham
- Assignee: ATI Technologies ULC
- Current Assignee: ATI Technologies ULC
- Current Assignee Address: CA Markham
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F12/1027 ; G06F8/41

Abstract:
A processing system includes a hardware translation lookaside buffer (TLB) retry loop that retries virtual memory address to physical memory address translation requests from a software client independent of a command from the software client. In response to a retry response notification at the TLB, a controller of the TLB waits for a programmable delay period and then retries the request without involvement from the software client. After a retry results in a hit at the TLB, the controller notifies the software client of the hit. Alternatively, if a retry results in an error at the TLB, the controller notifies the software client of the error and the software client initiates error handling.
Public/Granted literature
- US20230153249A1 HARDWARE TRANSLATION REQUEST RETRY MECHANISM Public/Granted day:2023-05-18
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