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公开(公告)号：US11640711B2
公开(公告)日：2023-05-02
申请号：US17030250
申请日：2020-09-23
发明人： Nicholas Malaya , Max Kiehn
摘要： A technique for generating a trained discriminator is provided. The technique includes applying one or more of a glitched image or an unglitched image to a discriminator; receiving classification output from the discriminator; adjusting weights of the discriminator to improve classification accuracy of the discriminator; applying noise to a generator; receiving an output image from the generator; applying the output image to the discriminator to obtain a classification; and adjusting weights of one of the discriminator or the generator to improve ability of the generator to reduce classification accuracy of the discriminator, based on the classification.
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公开(公告)号：US11631187B2
公开(公告)日：2023-04-18
申请号：US17031645
申请日：2020-09-24
摘要： Systems, apparatuses, and methods for implementing a depth buffer pre-pass are disclosed. A rendering application uses a binning approach to render primitives of a virtual scene on a tile-by-tile basis, with each tile corresponding to a portion of the screen. The application causes a depth buffer pre-pass to be performed for the primitives of the tile before a pixel shader is invoked. During the depth buffer pre-pass, only the depth part of the virtual scene is rendered to determine which pixel samples are visible and which pixel samples are hidden. Then, the scene is redrawn, but the pixel samples that are hidden are not sent to the pixel shader. In cases where a relatively large percentage of primitives overlap, this technique increases the efficiency of the rendering application since pixel shading can be avoided for the pixel samples that are hidden.
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公开(公告)号：US11630715B2
公开(公告)日：2023-04-18
申请号：US17131512
申请日：2020-12-22
摘要： A method and system for recording and logging errors in a computer system includes reading first error handling information with respect to a transaction. The first error handling information is stored in a first component, and based upon a condition of the storage in the first component, an oldest error information is evicted from the first component.
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公开(公告)号：US20230102063A1
公开(公告)日：2023-03-30
申请号：US17487480
申请日：2021-09-28
摘要： An optimized service-based pipeline includes a resource manager that receives a request that includes a description of a workload from a workload initiator such as an application. The resource manager identifies runtime utilization metrics of a plurality of processing resources, where the plurality of processing resources includes at least a first graphics processing unit (GPU) and a second GPU. The resource manager determines, based on the utilization metrics and one or more policies, a workload allocation recommendation for the workload. Thus, the workload initiator can determine whether placing a workload on a particular processing resource is preferable based on runtime behavior of the system and policies established of the workload.
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公开(公告)号：US20230099455A1
公开(公告)日：2023-03-30
申请号：US17490303
申请日：2021-09-30
申请人： ATI Technologies ULC
发明人： Kamraan Nasim , Erez Koelewyn , Shadi Dashmiz
IPC分类号： G06F9/4401 , H04L9/32
摘要： Techniques described herein provide users with the ability to persistently adjust settings for boot-time features (BTF) of a computing device. A user requests a particular BTF configuration adjustment for a device via a device driver. The driver instructs trusted firmware of the device to store a boot override record in persistent storage accessible by a bootloader for the device. Upon implementation of the boot sequence for the device, the bootloader applies the changes reflected in the record to BTF configuration data. The boot override information is persistently available to the bootloader, which ensures that the configuration changes that the boot override record(s) represent are applied to the BTFs of the device until the boot override record(s) are cleared or invalidated. Further, to ensure the security of boot override record(s), the trusted firmware generates, for each record, an HMAC tag using an HMAC key derived from a Chip Endorsement Fused Secret from the hardware.
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公开(公告)号：US20230096874A1
公开(公告)日：2023-03-30
申请号：US17488982
申请日：2021-09-29
申请人： ATI Technologies ULC
发明人： Keith Lee , Edward George Callway , Isobel Lees
摘要： Systems, apparatuses, and methods for implementing content adaptive processing via ringing estimation and suppression are disclosed. A ring estimator estimates the amount of ringing when a wide filter kernel is used for image processing. The amount of ringing can be specified as an under-shoot or an over-shoot. A blend factor calculation unit determines if the estimated amount of ringing is likely to be visually objectionable. If the ringing is likely to be visually objectionable, then the blend factor calculation unit generates a blend factor value to suppress the objectionable ringing. The blend factor value is generated for each set of source pixels based on this determination. The blend factor value is then applied to how the blending is mixed between narrow and wide filters for the corresponding set of source pixels. The preferred blending between the narrow and wide filters is changeable on a pixel-by-pixel basis during image processing.
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公开(公告)号：US20230078439A1
公开(公告)日：2023-03-16
申请号：US17992451
申请日：2022-11-22
IPC分类号： G06F21/74 , G06F21/57 , H04L67/104 , G06F13/42 , G06F15/78
摘要： Devices, methods, and systems for secure communications on a computing device. A host operating system (OS) runs on a host processor in communication with a host memory. A secure OS runs on a coprocessor in communication with a secure memory. The coprocessor receives information from an external device over a secure peer-to-peer (P2P) connection. The secure P2P connection is managed by the secure OS and is not accessible by the host OS.
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公开(公告)号：US11605149B2
公开(公告)日：2023-03-14
申请号：US17708500
申请日：2022-03-30
申请人： ATI Technologies ULC
摘要： A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
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9.发明申请公开(公告)号：US20230053263A1
公开(公告)日：2023-02-16
申请号：US17884793
申请日：2022-08-10
申请人： ATI TECHNOLOGIES ULC
发明人： David I.J. GLEN
摘要： A graphics processing unit (GPU) includes a timing reference one or more processors configured to generate and provide, based on the timing reference, frames to a display system that supports variable refresh rates. The frames include a vertical blanking region having a first duration. The display system transmits information indicating an operation to be performed by the display system during the vertical blanking region of one or more subsequent frames. The one or more processors are configured to increase the first duration to a second duration in response to receiving the information indicating an operation to be performed by the display system during the vertical blanking region of at least one subsequent frame. In some cases, the first duration of the vertical blanking region is a minimum duration that corresponds to a maximum refresh rate supported by the display system.
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公开(公告)号：US11568527B2
公开(公告)日：2023-01-31
申请号：US17031076
申请日：2020-09-24
申请人： ATI TECHNOLOGIES ULC
发明人： Feng Pan , Yang Liu , Crystal Sau , Wei Gao , Mingkai Shao , Dong Liu , Ihab Amer , Gabor Sines
摘要： Calculating, for each frame of a plurality of frames, a corresponding quality value; calculating, for each frame of the plurality of frames, based on one or more visual attributes of a frame, a weight for the corresponding quality value of the frame; calculating an aggregate quality value for the plurality of frames based on the weight and the corresponding quality value for each frame of the plurality of frames; and providing an assessment of the plurality of frames based on the aggregate quality value for the plurality of frames.
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