Invention Grant
- Patent Title: Systems and methods for PLL gain calibration
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Application No.: US18121404Application Date: 2023-03-14
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Publication No.: US12132490B2Publication Date: 2024-10-29
- Inventor: Karim M Megawer , Jongmin Park , Thomas Mayer
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Fletcher Yoder, P.C.
- Main IPC: H03L7/083
- IPC: H03L7/083 ; H03L7/081 ; H03L7/195

Abstract:
This disclosure is directed to PLLs, and, in particular, to enhancing PLL performance via gain calibration. PLL loop gain may vary with respect to process, voltage, and temperature (PVT) variation. To control the PLL loop gain, a gain calibration loop may be implemented. However, calibrating the loop gain by directly measuring the loop gain may be disadvantageous. To reduce or eliminate PLL loop gain variation due to PVT variation, a PLL having a loop gain function that is a function of an input phase offset time with a phase noise performance that remains consistent across PVT variations is disclosed. By determining a relationship between PLL loop gain and phase offset, detecting and calibrating phase offset may result in enhanced calibration of the PLL loop gain, while avoiding the additional difficulty and complexity associated with directly measuring loop gain of a PLL.
Public/Granted literature
- US20240313789A1 SYSTEMS AND METHODS FOR PLL GAIN CALIBRATION Public/Granted day:2024-09-19
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