A display panel includes: a base substrate including a display region and a fan-out region, and the fan-out region is located between the display region and a chip; a plurality of data wires/touch wires located in the fan-out region for respectively electrically connecting a plurality of data lines/touch signal lines with the chip. A portion of the plurality of data wires is located in a first conductive layer while a rest portion thereof is located in the second conductive layer. A portion of the plurality of touch wires is located in at least one of the first conductive layer and the second conductive layer while a rest portion thereof is located in the third conductive layer. A pitch between any two adjacent wires in the first/second/third conductive layer is a first/second/third wire pitch, respectively. The first wire pitch and the second wire pitch are smaller than the third wire pitch.