A stage circuit includes an input unit connected to a first input terminal receiving a gate start pulse or a previous stage carry signal to control a voltage of a first node, a first output unit connected to a fourth input terminal to which a clock signal is input and supplying a scan signal to a first output terminal corresponding to a voltage of the first node and a second node, a second output unit connected to a third input terminal to which a second carry clock signal is input and supplying a carry signal to a second output terminal corresponding to the voltage of the first node and the second node, a first control unit connected to a first power input terminal to which first power is input and controlling a voltage of a third node, and a second control unit connected to a second power input terminal.