Invention Grant
- Patent Title: Structure and method for multigate devices with suppressed diffusion
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Application No.: US17464207Application Date: 2021-09-01
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Publication No.: US12159924B2Publication Date: 2024-12-03
- Inventor: Chih-Hsuan Chen , Wen-Chun Keng , Yu-Kuan Lin , Shih-Hao Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: HAYNES AND BOONE, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/02 ; H01L29/06 ; H01L29/423 ; H01L29/786 ; H10B10/00

Abstract:
A method includes forming a fin that includes a first semiconductor layers and a second semiconductor layers alternatively disposed; forming a gate stack on the fin and a gate spacer disposed on a sidewall of the gate stack; etching the fin within a source/drain region, resulting in a source/drain trench; recessing the first semiconductor layers in the source/drain trench, resulting in first recesses underlying the gate spacer; forming inner spacers in the first recesses; recessing the second semiconductor layers in the source/drain trench, resulting in second recesses; and epitaxially growing a source/drain feature in the source/drain trench, wherein the epitaxially growing further includes a first epitaxial semiconductor layer extending into the second recesses; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer and filling in the source/drain trench, wherein the first and second epitaxial semiconductor layers are different in composition.
Public/Granted literature
- US20220367683A1 Structure and Method for Multigate Devices with Suppressed Diffusion Public/Granted day:2022-11-17
Information query
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