公开(公告)号：US20240379801A1

公开(公告)日：2024-11-14

申请号：US18782515

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Hsuan Chen ,  Ping-Wei Wang

IPC: H01L29/423 ,  H01L21/265 ,  H01L21/308 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.

公开(公告)号：US11742416B2

公开(公告)日：2023-08-29

申请号：US17332025

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Chia-Hung Chou ,  Chih-Hsuan Chen ,  Ping-En Cheng ,  Hsin-Wen Su ,  Chien-Chih Lin ,  Szu-Chi Yang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/66553 ,  H01L29/7851

Abstract: A semiconductor structure includes: a semiconductor substrate; a first source/drain feature and a second source/drain feature over the semiconductor substrate; and semiconductor layers extending longitudinally in a first direction and connecting the first source/drain feature and the second source/drain feature. The semiconductor layers are spaced apart from each other in a second direction perpendicular to the first direction. The semiconductor structure further includes inner spacers each between two adjacent semiconductor layers; metal oxide layers interposing between the inner spacers and the semiconductor layers; and a gate structure wrapping around the semiconductor layers and the metal oxide layers.

公开(公告)号：US20230066387A1

公开(公告)日：2023-03-02

申请号：US17461572

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsuan Chen ,  Chia-Hao Pao ,  Shih-Hao Lin

IPC: H01L27/11

Abstract: A Static Radom Access Memory (SRAM) cell includes a pass-gate transistor and a pull-down transistor. The pass-gate transistor includes a first active region and a first gate structure engaging the first active region. The pull-down transistor includes a second active region and a second gate structure engaging the second active region. The SRAM cell further includes a first isolation feature abutting the first gate structure and a second isolation feature abutting the second gate structure. The first isolation feature is spaced from the first active region of the pass-gate transistor for a first distance. The second isolation feature is spaced from the second active region of the pull-down transistor for a second distance that is larger than the first distance.

公开(公告)号：US12219747B2

公开(公告)日：2025-02-04

申请号：US17401151

申请日：2021-08-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Chih-Hsuan Chen ,  Kian-Long Lim ,  Chao-Yuan Chang ,  Feng-Ming Chang ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H10B10/00 ,  G06F30/392 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a β ratio of an SRAM cell.

公开(公告)号：US20230061384A1

公开(公告)日：2023-03-02

申请号：US17462709

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Chih-Hsuan Chen ,  Chih-Chuan Yang ,  Shih-Hao Lin

IPC: H01L27/088 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/8234

Abstract: A device includes a first and a second stacks of channel layers each extending from a first height to a second height. A first dielectric feature on a first side of the first stack and between the first and the second stacks extends from a third height to a fourth height. A second dielectric feature on a second side of the first stack opposite to the first side extends from the third height to a fifth height. A gate electrode extends continuously across a top surface of the first and the second stacks and extends to a sixth height. The fifth height is above the sixth height, the sixth height is above the second height, the second height is above the fourth height, the fourth height is above the first height, and the first height is above the third height.

公开(公告)号：US20230046028A1

公开(公告)日：2023-02-16

申请号：US17401151

申请日：2021-08-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Chih-Hsuan Chen ,  Kian-Long Lim ,  Chao-Yuan Chang ,  Feng-Ming Chang ,  Lien Jung Hung ,  Ping-Wei Wang

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  G06F30/392

Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a β ratio of an SRAM cell.

公开(公告)号：US12159924B2

公开(公告)日：2024-12-03

申请号：US17464207

申请日：2021-09-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsuan Chen ,  Wen-Chun Keng ,  Yu-Kuan Lin ,  Shih-Hao Lin

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H10B10/00

Abstract: A method includes forming a fin that includes a first semiconductor layers and a second semiconductor layers alternatively disposed; forming a gate stack on the fin and a gate spacer disposed on a sidewall of the gate stack; etching the fin within a source/drain region, resulting in a source/drain trench; recessing the first semiconductor layers in the source/drain trench, resulting in first recesses underlying the gate spacer; forming inner spacers in the first recesses; recessing the second semiconductor layers in the source/drain trench, resulting in second recesses; and epitaxially growing a source/drain feature in the source/drain trench, wherein the epitaxially growing further includes a first epitaxial semiconductor layer extending into the second recesses; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer and filling in the source/drain trench, wherein the first and second epitaxial semiconductor layers are different in composition.

公开(公告)号：US20240339449A1

公开(公告)日：2024-10-10

申请号：US18748200

申请日：2024-06-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Chih-Chuan Yang ,  Chih-Hsuan Chen ,  Shih-Hao Lin

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: A device includes a first and a second stacks of channel layers each extending from a first height to a second height. A first dielectric feature on a first side of the first stack and between the first and the second stacks extends from a third height to a fourth height. A second dielectric feature on a second side of the first stack opposite to the first side extends from the third height to a fifth height. A gate electrode extends continuously across a top surface of the first and the second stacks and extends to a sixth height. The fifth height is above the sixth height, the sixth height is above the second height, the second height is above the fourth height, the fourth height is above the first height, and the first height is above the third height.

公开(公告)号：US12040325B2

公开(公告)日：2024-07-16

申请号：US17462709

申请日：2021-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Chih-Hsuan Chen ,  Chih-Chuan Yang ,  Shih-Hao Lin

IPC: H01L29/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: A device includes a first and a second stacks of channel layers each extending from a first height to a second height. A first dielectric feature on a first side of the first stack and between the first and the second stacks extends from a third height to a fourth height. A second dielectric feature on a second side of the first stack opposite to the first side extends from the third height to a fifth height. A gate electrode extends continuously across a top surface of the first and the second stacks and extends to a sixth height. The fifth height is above the sixth height, the sixth height is above the second height, the second height is above the fourth height, the fourth height is above the first height, and the first height is above the third height.

公开(公告)号：US20220367683A1

公开(公告)日：2022-11-17

申请号：US17464207

申请日：2021-09-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsuan Chen ,  Wen-Chun Keng ,  Yu-Kuan Lin ,  Shih-Hao Lin

IPC: H01L29/66 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02

Abstract: A method includes forming a fin that includes a first semiconductor layers and a second semiconductor layers alternatively disposed; forming a gate stack on the fin and a gate spacer disposed on a sidewall of the gate stack; etching the fin within a source/drain region, resulting in a source/drain trench; recessing the first semiconductor layers in the source/drain trench, resulting in first recesses underlying the gate spacer; forming inner spacers in the first recesses; recessing the second semiconductor layers in the source/drain trench, resulting in second recesses; and epitaxially growing a source/drain feature in the source/drain trench, wherein the epitaxially growing further includes a first epitaxial semiconductor layer extending into the second recesses; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer and filling in the source/drain trench, wherein the first and second epitaxial semiconductor layers are different in composition.