Invention Grant
- Patent Title: Buffer display data in a chiplet architecture
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Application No.: US18146811Application Date: 2022-12-27
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Publication No.: US12164365B2Publication Date: 2024-12-10
- Inventor: Gia Tung Phan , Ashish Jain , Shang Yang
- Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
- Applicant Address: US CA Santa Clara; CA Markham
- Assignee: Advanced Micro Devices, Inc.,ATI Technologies ULC
- Current Assignee: Advanced Micro Devices, Inc.,ATI Technologies ULC
- Current Assignee Address: US CA Santa Clara; CA Markham
- Agency: Kowert, Hood, Munyon, Rankin & Goetzel, P.C.
- Agent Rory D. Rankin
- Main IPC: G06F1/3296
- IPC: G06F1/3296 ; G06F12/0875 ; G06T1/20 ; G06T1/60

Abstract:
An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among at least two of the multiple functional blocks. In one implementation, a prior static allocation determines that only a subset of the functional blocks store the data of the given type. In another implementation, each of the functional blocks stores the data of the given type, and when an idle state has occurred, data of the given type is moved between the multiple functional blocks until one or more functional blocks no longer store data of the given type. When a transition to the idle state has occurred, the functional blocks that do not store the data of the given type are transitioned to a sleep state.
Public/Granted literature
- US20240211023A1 BUFFER DISPLAY DATA IN A CHIPLET ARCHITECTURE Public/Granted day:2024-06-27
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