Invention Grant
- Patent Title: Channel routing for simultaneous switching outputs
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Application No.: US17849197Application Date: 2022-06-24
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Publication No.: US12176065B2Publication Date: 2024-12-24
- Inventor: Xuan Chen , Chih-Hua Hsu , Pradeep Jayaraman , Abdussalam Aburwein
- Applicant: ATI Technologies ULC , Advanced Micro Devices, Inc.
- Applicant Address: CA Markham; US CA Santa Clara
- Assignee: ATI Technologies ULC,Advanced Micro Devices, Inc.
- Current Assignee: ATI Technologies ULC,Advanced Micro Devices, Inc.
- Current Assignee Address: CA Markham; US CA Santa Clara
- Agency: Polansky & Associates, P.L.L.C.
- Agent Paul J. Polansky
- Main IPC: G11C7/22
- IPC: G11C7/22 ; G11C5/02 ; G11C7/10 ; G11C8/18

Abstract:
A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory accessing agent generates generating memory access requests including first memory access requests that access the memory. The memory controller provides memory commands to the memory in response to the first memory access requests. The data fabric routes the first memory access requests to a first downstream port in response to a corresponding first memory request accessing the first pseudo channel, and to a second downstream port in response to the corresponding first memory request accessing the second pseudo channel. The memory controller has first and second upstream ports coupled to the first and second downstream ports of the data fabric, respectively, and a downstream port coupled to the memory.
Public/Granted literature
- US20230420018A1 CHANNEL ROUTING FOR SIMULTANEOUS SWITCHING OUTPUTS Public/Granted day:2023-12-28
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