- Patent Title: Block family error avoidance bin scans after memory device power-on
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Application No.: US17898725Application Date: 2022-08-30
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Publication No.: US12183413B2Publication Date: 2024-12-31
- Inventor: Guang Hu
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: LOWENSTEIN SANDLER LLP
- Main IPC: G11C29/02
- IPC: G11C29/02 ; G11C29/04 ; G11C29/52

Abstract:
A method includes, in response to detecting a power on event, selecting a block from a set of blocks, causing a first scan to be performed using a set of read level offsets to select, from a set of bins in accordance with a scan order, a first bin assigned with a first read level offset resulting in a first bit error metric value, in response to determining that the first bin is not an initial bin of the scan order, causing, using a second read level offset assigned to a second bin, a second scan to be performed to obtain a second bit error metric value, wherein the second bin immediately precedes the first bin in the scan order, and selecting, based on first bit error metric value and the second bit error metric value, an optimal bin from the set of bins.
Public/Granted literature
- US20240071554A1 BLOCK FAMILY ERROR AVOIDANCE BIN SCANS AFTER MEMORY DEVICE POWER-ON Public/Granted day:2024-02-29
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