Invention Grant
- Patent Title: Integrated circuit with latch-up immunity
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Application No.: US17840913Application Date: 2022-06-15
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Publication No.: US12191306B2Publication Date: 2025-01-07
- Inventor: Jing-Yi Lin , Chih-Chuan Yang , Shih-Hao Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8238 ; H01L27/02

Abstract:
Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming an epitaxial structure having a first doping type over a first portion of a semiconductor substrate. A second portion of the semiconductor substrate is formed over the epitaxial structure and the first portion of the semiconductor substrate. A first doped region having the first doping type is formed in the second portion of the semiconductor substrate and directly over the epitaxial structure. A second doped region having a second doping type opposite the first doping type is formed in the second portion of the semiconductor substrate, where the second doped region is formed on a side of the epitaxial structure. A plurality of fins of the semiconductor substrate are formed by selectively removing portions of the second portion of the semiconductor substrate.
Public/Granted literature
- US20220310599A1 INTEGRATED CIRCUIT WITH LATCH-UP IMMUNITY Public/Granted day:2022-09-29
Information query
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