Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Spike current suppression is implemented using a folded access line structure. Each access line includes integrated top and bottom insulating layers that restrict current flow to the memory cells through a narrower middle portion of the access line. For near memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the meandering, folded circuit path that flows through the middle portion. Spike discharge that occurs when the memory cell is selected is reduced by this higher resistance path.