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公开(公告)号：US20220319592A1
公开(公告)日：2022-10-06
申请号：US17222864
申请日：2021-04-05
Applicant: Micron Technology, Inc.
Inventor： Sundaravadivel Rajarajan , Srivatsan Venkatesan , Iniyan Soundappa Elango , Robert Douglas Cassel
Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.
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公开(公告)号：US20250085887A1
公开(公告)日：2025-03-13
申请号：US18777273
申请日：2024-07-18
Applicant: Micron Technology, Inc.
Inventor： Srivatsan Venkatesan , Kaveri Jain , Salil Shashikant Mujumdar , Rajat Vishnoi , Sushma Dogiparthi
Abstract: An inductor is formed on an integrated circuit (IC) using one or more structures formed during or in coordination with 3D NAND structure fabrication with one or more modifications. The inductor has a staircase structure, the staircase structure having a plurality of tiers that form steps on one side of the staircase structure. Each tier comprises a conductive layer. The plurality of tiers includes at least a first tier and a second tier. The inductor has a first contact electrically coupling the first tier and the second tier. A first portion of a die is occupied by a memory sub-component comprising at least one three-dimensional (3D) NAND memory component and a second portion of the die is occupied by the inductor.
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公开(公告)号：US20220319594A1
公开(公告)日：2022-10-06
申请号：US17824826
申请日：2022-05-25
Applicant: Micron Technology, Inc.
Inventor： Srivatsan Venkatesan , Sundaravadivel Rajarajan , Iniyan Soundappa Elango , Robert Douglas Cassel
Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. Spike current suppression is implemented by charge screening structures. The charge screening structures are formed by laterally integrating insulating layers into selected interior regions of the left and/or right portions of the access line. The insulating layers vertically separate the access line into top and bottom conductive portions above and below the insulating layers. For memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the top or bottom conductive portion. During a spike discharge, charge is choked by this higher resistance path. This suppresses spike current that occurs when the memory cell is selected.
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公开(公告)号：US12219782B2
公开(公告)日：2025-02-04
申请号：US17536927
申请日：2021-11-29
Applicant: Micron Technology, Inc.
Inventor： Srivatsan Venkatesan , Fabio Pellizzer
Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Spike current suppression is implemented using a folded access line structure. Each access line includes integrated top and bottom insulating layers that restrict current flow to the memory cells through a narrower middle portion of the access line. For near memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the meandering, folded circuit path that flows through the middle portion. Spike discharge that occurs when the memory cell is selected is reduced by this higher resistance path.
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公开(公告)号：US20230069190A1
公开(公告)日：2023-03-02
申请号：US17460042
申请日：2021-08-27
Applicant: Micron Technology, Inc.
Inventor： Sateesh Talasila , Chandrasekhar Mandalapu , Robert Douglas Cassel , Sundaravadivel Rajarajan , Iniyan Soundappa Elango , Srivatsan Venkatesan
IPC: G11C13/00
Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a crosspoint memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is formed of a conductive material (e.g., tungsten). The access line includes one or more resistive layers (e.g., tungsten silicon nitride) each having a resistivity greater than the resistivity of the conductive material used to form the access line. The resistive layers are formed overlying or underlying at least a portion of the memory cells. A driver is electrically connected to the access line using a via. The driver generates a voltage on the access line to access the memory cells.
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Patent Agency Ranking
公开(公告)号：US20230018390A1
公开(公告)日：2023-01-19
申请号：US17943520
申请日：2022-09-13
Applicant: Micron Technology, Inc.
Inventor： Sundaravadivel Rajarajan , Srivatsan Venkatesan , Iniyan Soundappa Elango , Robert Douglas Cassel
Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is split into left and right portions. Each portion is electrically connected to a single via, which a driver uses to generate a voltage on the access line. To reduce electrical discharge associated with current spikes, a first resistor is located between the left portion and the via, and a second resistor is located between the right portion and the via.
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公开(公告)号：US20250142838A1
公开(公告)日：2025-05-01
申请号：US19004126
申请日：2024-12-27
Applicant: Micron Technology, Inc.
Inventor： Srivatsan Venkatesan , Fabio Pellizzer
Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Spike current suppression is implemented using a folded access line structure. Each access line includes integrated top and bottom insulating layers that restrict current flow to the memory cells through a narrower middle portion of the access line. For near memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the meandering, folded circuit path that flows through the middle portion. Spike discharge that occurs when the memory cell is selected is reduced by this higher resistance path.
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公开(公告)号：US11984161B2
公开(公告)日：2024-05-14
申请号：US17824826
申请日：2022-05-25
Applicant: Micron Technology, Inc.
Inventor： Srivatsan Venkatesan , Sundaravadivel Rajarajan , Iniyan Soundappa Elango , Robert Douglas Cassel
CPC classification number: G11C13/0059 , G11C13/0004 , G11C13/003 , H10B63/24 , H10B63/80 , H10N70/063 , H10N70/231 , H10N70/882 , G11C2213/72
Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. Spike current suppression is implemented by charge screening structures. The charge screening structures are formed by laterally integrating insulating layers into selected interior regions of the left and/or right portions of the access line. The insulating layers vertically separate the access line into top and bottom conductive portions above and below the insulating layers. For memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the top or bottom conductive portion. During a spike discharge, charge is choked by this higher resistance path. This suppresses spike current that occurs when the memory cell is selected.
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公开(公告)号：US11862215B2
公开(公告)日：2024-01-02
申请号：US17460042
申请日：2021-08-27
Applicant: Micron Technology, Inc.
Inventor： Sateesh Talasila , Chandrasekhar Mandalapu , Robert Douglas Cassel , Sundaravadivel Rajarajan , Iniyan Soundappa Elango , Srivatsan Venkatesan
CPC classification number: G11C13/003 , G11C13/004 , G11C13/0026 , G11C13/0038 , G11C13/0069
Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is formed of a conductive material (e.g., tungsten). The access line includes one or more resistive layers (e.g., tungsten silicon nitride) each having a resistivity greater than the resistivity of the conductive material used to form the access line. The resistive layers are formed overlying or underlying at least a portion of the memory cells. A driver is electrically connected to the access line using a via. The driver generates a voltage on the access line to access the memory cells.
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公开(公告)号：US11715520B2
公开(公告)日：2023-08-01
申请号：US17222870
申请日：2021-04-05
Applicant: Micron Technology, Inc.
Inventor： Robert Douglas Cassel , Sundaravadivel Rajarajan , Srivatsan Venkatesan , Iniyan Soundappa Elango
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/004 , G11C13/0026 , G11C13/0028 , G11C13/0038 , H10B63/80 , H10N70/023 , H10N70/063 , H10N70/066 , H10N70/068 , H10N70/231 , H10N70/883
Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line has left and right portions. A conductive layer is positioned in the access line between the left and right portions. The conductive layer is formed in a socket that has been etched or otherwise formed in the access line to provide an opening. This opening is filled by the conductive layer. The conductive layer electrically connects the left and right portions of the access line to a via. A driver is electrically connected to the via for generating a voltage on the access line for accessing one or more memory cells. To reduce electrical discharge associated with current spikes, a first resistive film is formed in the access line between the left portion and the conductive layer, and a second resistive film is formed in the access line between the right portion and the conductive layer.
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