An apparatus includes one or more processors and a memory having instructions stored thereon that, when executed by the one or more processors, cause the apparatus to receive a first wake-up signal. The first wake-up signal is one of K wake-up signals, K is an integer greater than or equal to 1, and the K wake-up signals are quasi co-located with K synchronization signal blocks (SSBs), K channel state information-reference signals (CSI-RSs), or K demodulation reference signals (DMRSs). The apparatus is also caused to determine M paging occasions. There is a correspondence between the K wake-up signals and the M paging occasions, and M is an integer greater than or equal to 1. The apparatus is further caused to receive, on the M paging occasions, downlink control information (DCI) used for paging.