Invention Grant
- Patent Title: Arsenic diffusion profile engineering for transistors
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Application No.: US17628634Application Date: 2020-07-01
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Publication No.: US12249626B2Publication Date: 2025-03-11
- Inventor: Patricia M. Liu , Flora Fong-Song Chang , Zhiyuan Ye
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan, LLP
- International Application: PCT/US2020/040535 WO 20200701
- International Announcement: WO2021/021381 WO 20210204
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/02 ; H01L21/22 ; H01L29/167 ; H01L29/66 ; H01L29/78

Abstract:
Embodiments of the present disclosure relate to methods for forming a source/drain extension. In one embodiment, a method for forming an nMOS device includes forming a gate electrode and a gate spacer over a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to expose a side wall and a bottom, forming a silicon arsenide (Si:As) layer on the side wall and the bottom, and forming a source/drain region on the Si:As layer. During the deposition of the Si:As layer and the formation of the source/drain region, the arsenic dopant diffuses from the Si:As layer into a third portion of the semiconductor fin located below the gate spacer, and the third portion becomes a doped source/drain extension region. By utilizing the Si:As layer, the doping of the source/drain extension region is controlled, leading to reduced contact resistance while reducing dopants diffusing into the channel region.
Public/Granted literature
- US20220320294A1 ARSENIC DIFFUSION PROFILE ENGINEERING FOR TRANSISTORS Public/Granted day:2022-10-06
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