公开(公告)号：US12297559B2

公开(公告)日：2025-05-13

申请号：US17961463

申请日：2022-10-06

Applicant: Applied Materials, Inc.

Inventor： Abhishek Dube ,  Xuebin Li ,  Hua Chung ,  Flora Fong-Song Chang

IPC: C30B25/18 ,  C23C16/02 ,  C23C16/24 ,  C23C16/54 ,  C23C16/56 ,  C30B29/06 ,  C30B33/12 ,  H01J37/32 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/687

Abstract: Embodiments of the present disclosure generally relate to methods for forming epitaxial layers on a semiconductor device. In one or more embodiments, methods include removing oxides from a substrate surface during a cleaning process, flowing a processing reagent containing a silicon source and exposing the substrate to the processing reagent during an epitaxy process, and stopping the flow of the processing reagent. The method also includes flowing a purging gas and pumping residues from the processing system, stopping the flow of the purge gas, flowing an etching gas and exposing the substrate to the etching gas. The etching gas contains hydrogen chloride and at least one germanium and/or chlorine compound. The method further includes stopping the flow of the at least one compound while continuing the flow of the hydrogen chloride and exposing the substrate to the hydrogen chloride and stopping the flow of the hydrogen chloride.

公开(公告)号：US12196617B2

公开(公告)日：2025-01-14

申请号：US17609335

申请日：2020-06-29

Applicant: Applied Materials, Inc.

Inventor： Zuoming Zhu ,  Shu-Kwan Lau ,  Enle Choo ,  Ala Moradian ,  Flora Fong-Song Chang ,  Maxim D. Shaposhnikov ,  Bindusagar Marath Sankarathodi ,  Zhepeng Cong ,  Zhiyuan Ye ,  Vilen K. Nestorov ,  Surendra Singh Srivastava ,  Saurabh Chopra ,  Patricia M. Liu ,  Errol Antonio C. Sanchez ,  Jenny C. Lin ,  Schubert S. Chu

IPC: G01J5/00 ,  H01L21/67

Abstract: An apparatus for controlling temperature profile of a substrate within an epitaxial chamber includes a bottom center pyrometer and a bottom outer pyrometer to respectively measure temperatures at a center location and an outer location of a first surface of a susceptor of an epitaxy chamber, a top center pyrometer and a top outer pyrometer to respectively measure temperatures at a center location and an outer location of a substrate disposed on a second surface of the susceptor opposite the first surface, a first controller to receive signals, from the bottom center pyrometer and the bottom outer pyrometer, and output a feedback signal to a first heating lamp module that heats the first surface based on the measured temperatures of the first surface, and a second controller to receive signals, from the top center pyrometer, the top outer pyrometer, the bottom center pyrometer, and the bottom outer pyrometer, and output a feedback signal to a second heating lamp module that heats the substrate based on the measured temperatures of a substrate and the measured temperatures of the first surface.

公开(公告)号：US12249626B2

公开(公告)日：2025-03-11

申请号：US17628634

申请日：2020-07-01

Applicant: Applied Materials, Inc.

Inventor： Patricia M. Liu ,  Flora Fong-Song Chang ,  Zhiyuan Ye

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/22 ,  H01L29/167 ,  H01L29/66 ,  H01L29/78

Abstract: Embodiments of the present disclosure relate to methods for forming a source/drain extension. In one embodiment, a method for forming an nMOS device includes forming a gate electrode and a gate spacer over a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to expose a side wall and a bottom, forming a silicon arsenide (Si:As) layer on the side wall and the bottom, and forming a source/drain region on the Si:As layer. During the deposition of the Si:As layer and the formation of the source/drain region, the arsenic dopant diffuses from the Si:As layer into a third portion of the semiconductor fin located below the gate spacer, and the third portion becomes a doped source/drain extension region. By utilizing the Si:As layer, the doping of the source/drain extension region is controlled, leading to reduced contact resistance while reducing dopants diffusing into the channel region.

公开(公告)号：US11195914B2

公开(公告)日：2021-12-07

申请号：US16588901

申请日：2019-09-30

Applicant: Applied Materials, Inc.

Inventor： Patricia M. Liu ,  Flora Fong-Song Chang ,  Zhiyuan Ye

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/24

Abstract: Embodiments of the present disclosure relate to a transistor and methods for forming a transistor. A transistor includes a gate electrode structure disposed over a channel region, a source/drain extension region disposed adjacent to the channel region, and a source/drain region disposed on the source/drain extension region. The source/drain region includes antimony (Sb). The method of forming a transistor includes forming the source/drain extension region and forming the source/drain region on the source/drain extension region. The antimony helps prevent unwanted migration of dopants from the source/drain region to the source/drain extension region.

公开(公告)号：US12165934B2

公开(公告)日：2024-12-10

申请号：US16938510

申请日：2020-07-24

Applicant: Applied Materials, Inc.

Inventor： Zuoming Zhu ,  Shu-Kwan Lau ,  Ala Moradian ,  Enle Choo ,  Flora Fong-Song Chang ,  Vilen K Nestorov ,  Zhiyuan Ye ,  Bindusagar Marath Sankarathodi ,  Maxim D. Shaposhnikov ,  Surendra Singh Srivastava ,  Zhepeng Cong ,  Patricia M. Liu ,  Errol C. Sanchez ,  Jenny C. Lin ,  Schubert S. Chu ,  Balakrishnam R. Jampana

IPC: H01L21/66 ,  H01L21/67

Abstract: A method for processing a substrate within a processing chamber comprises receiving a first radiation signal corresponding to a film on a target element disposed within the processing chamber, analyzing the first radiation signal, and controlling the processing of the substrate based on the analyzed first radiation signal. The processing chamber includes a substrate support configured to support the substrate within a processing volume and a controller coupled to a first sensing device configured to receive the first radiation signal.

公开(公告)号：US11261538B1

公开(公告)日：2022-03-01

申请号：US17027385

申请日：2020-09-21

Applicant: Applied Materials, Inc.

Inventor： Ala Moradian ,  Zuoming Zhu ,  Patricia M. Liu ,  Shu-Kwan Lau ,  Flora Fong-Song Chang ,  Enle Choo ,  Zhiyuan Ye

IPC: C30B25/16 ,  H01L21/67 ,  C30B25/10

Abstract: The present invention provides methods and apparatus for processing semiconductor substrates in an epitaxy chamber configured to map a temperature profile for both substrates and interior chamber components. In one embodiment, the semiconductor processing chamber has a body having ceiling and a lower portion defining an interior volume. A substrate support is disposed in the interior volume. A mounting plate is coupled to the ceiling outside the interior volume. A movement assembly is coupled to the mounting plate. A sensor is coupled to the movement assembly and moveable relative to the ceiling. The sensor is configured to detect a temperature location in the interior volume.

公开(公告)号：US10276688B2

公开(公告)日：2019-04-30

申请号：US15896983

申请日：2018-02-14

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Zhiyuan Ye ,  Flora Fong-Song Chang ,  Abhishek Dube ,  Xuebin Li ,  Errol Antonio C. Sanchez ,  Hua Chung ,  Schubert S. Chu

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167 ,  H01L29/417 ,  H01L21/02

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.

公开(公告)号：US09923081B1

公开(公告)日：2018-03-20

申请号：US15479091

申请日：2017-04-04

Applicant: Applied Materials, Inc.

Inventor： Xinyu Bao ,  Zhiyuan Ye ,  Flora Fong-Song Chang ,  Abhishek Dube ,  Xuebin Li ,  Errol Antonio C. Sanchez ,  Hua Chung ,  Schubert S. Chu

IPC: H01L23/48 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167

CPC classification number: H01L29/6659 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7851

Abstract: A device comprising Si:As source and drain extensions and Si:As or Si:P source and drain features formed using selective epitaxial growth and a method of forming the same is provided. The epitaxial layers used for the source and drain extensions and the source and drain features herein are deposited by simultaneous film formation and film etching, wherein the deposited material on the monocrystalline layer is etched at a slower rate than deposition material deposited on non-monocrystalline location of a substrate. As a result, an epitaxial layer is deposited on the monocrystalline surfaces, and a layer is not deposited on non-monocrystalline surfaces of the same base material, such as silicon.