Invention Grant
- Patent Title: Mirror image of geometrical patterns in stacked integrated circuit dies
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Application No.: US17584450Application Date: 2022-01-26
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Publication No.: US12255178B2Publication Date: 2025-03-18
- Inventor: Ido Bourstein
- Applicant: Mellanox Technologies, Ltd.
- Applicant Address: IL Yokneam
- Assignee: Mellanox Technologies, Ltd.
- Current Assignee: Mellanox Technologies, Ltd.
- Current Assignee Address: IL Yokneam
- Agency: Meitar Patents Ltd.
- Agent Daniel Kligler
- Main IPC: H01L25/065
- IPC: H01L25/065 ; G03F1/20 ; H01L23/00

Abstract:
An electronic device includes a first integrated circuit (IC) die and a second IC die. The first IC die includes a first set of contact pads arranged in a first geometrical pattern on a first surface of the first IC die, the second IC die includes a second set of the contact pads that are arranged, on a second surface of the second IC die, in a second geometrical pattern that is a mirror image of the first geometrical pattern. The second surface of the second IC die is facing the first surface of the first IC die, and the contact pads of the first and second sets are aligned with one another and mounted on one another.
Public/Granted literature
- US20230238358A1 Stacking of integrated circuit dies Public/Granted day:2023-07-27
Information query
IPC分类: