Invention Grant
- Patent Title: Method of manufacturing integrated circuit using encapsulation during an etch process
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Application No.: US18526636Application Date: 2023-12-01
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Publication No.: US12290001B2Publication Date: 2025-04-29
- Inventor: Sanjeev Aggarwal , Sarin A. Deshpande , Kerry Joseph Nagel
- Applicant: Everspin Technologies, Inc.
- Applicant Address: US AZ Chandler
- Assignee: Everspin Technologies, Inc.
- Current Assignee: Everspin Technologies, Inc.
- Current Assignee Address: US AZ Chandler
- Agency: Bookoff McAndrews, PLLC
- Main IPC: H10N50/01
- IPC: H10N50/01 ; H10B61/00

Abstract:
A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.
Public/Granted literature
- US20240107891A1 METHOD OF MANUFACTURING INTEGRATED CIRCUIT USING ENCAPSULATION DURING AN ETCH PROCESS Public/Granted day:2024-03-28
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