Invention Application
- Patent Title: METHODS OF FORMING RECESSED HEMISPHERICAL GRAIN SILICON CAPACITOR STRUCTURES
- Patent Title (中): 形成残留的电化学硅电容器结构的方法
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Application No.: US09982294Application Date: 2001-10-16
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Publication No.: US20020028563A1Publication Date: 2002-03-07
- Inventor: Scott J. DeBoer
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: H01L021/20
- IPC: H01L021/20

Abstract:
Methods of manufacturing capacitor structures with edge zones that are substantially free of hemispherical grain silicon along the upper edges of the capacitor structures are disclosed. The resulting recessed hemispherical grain silicon layers reduce or prevent separation of particles from the hemispherical grain silicon layer during subsequent manufacturing processes, thereby reducing defects and increasing throughput. Among the methods of the present invention are methods of forming the capacitor structures in which the silicon layer used to form the hemispherical grain silicon is selectively doped. That selective doping provides an edge zone that does not convert to hemispherical grain silicon during manufacturing.
Public/Granted literature
- US06566222B2 Methods of forming recessed hemispherical grain silicon capacitor structures Public/Granted day:2003-05-20
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