公开(公告)号：US20020187654A1

公开(公告)日：2002-12-12

申请号：US10213812

申请日：2002-08-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. DeBoer ,  Randhir P.S. Thakur

IPC: H01L021/31 ,  H01L021/469 ,  C23C016/00

CPC classification number: H01L21/02183 ,  C23C16/40 ,  C23C16/52 ,  H01L21/02274 ,  H01L21/02356 ,  H01L21/316 ,  H01L21/31691 ,  H01L28/40 ,  H01L29/516

Abstract: A method of forming a high dielectric oxide film conventionally formed using a post formation oxygen anneal to reduce the leakage current of such film includes forming a high dielectric oxide film on a surface. The high dielectric oxide film has a dielectric constant greater than about 4 and includes a plurality of oxygen vacancies present during the formation of the film. The high dielectric oxide film is exposed during the formation thereof to an amount of atomic oxygen sufficient for reducing the number of oxygen vacancies and eliminating the post formation oxygen anneal of the high dielectric oxide film. Further, the amount of atomic oxygen used in the formation method may be controlled as a function of the amount of oxygen incorporated into the high dielectric oxide film during the formation thereof or be controlled as a function of the concentration of atomic oxygen in a process chamber in which the high dielectric oxide film is being formed. An apparatus for forming the high dielectric oxide film is also described.

Abstract translation: 使用后形成氧退火形成常规形成的高电介质氧化膜以减少这种膜的漏电流的方法包括在表面上形成高介电氧化物膜。 高电介质氧化物膜具有大于约4的介电常数，并且在膜的形成期间包括存在的多个氧空位。 高电介质氧化物膜在其形成期间暴露于足以减少氧空位数并且消除高电介质氧化物膜的后形成氧退火的原子氧量。 另外，形成方法中使用的原子氧的量可以作为在形成高电介质氧化物膜期间掺入到高电介质氧化膜中的氧的量的函数来控制，或者作为处理室中的原子氧浓度的函数来控制 其中形成高电介质氧化膜。 还描述了用于形成高电介质氧化物膜的装置。

公开(公告)号：US20010038111A1

公开(公告)日：2001-11-08

申请号：US09864552

申请日：2001-05-23

Applicant: Micron Technology, Inc.

Inventor： Scott J. DeBoer ,  Terry L. Gilton ,  Ceredig Roberts

IPC: H01L021/8234

CPC classification number: H01L21/76897 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76877 ,  H01L28/40 ,  H01L28/90

Abstract: An etching method includes providing a first insulating material layer on a substrate assembly surface and a second insulating material layer on the first insulating material layer. The first insulating material layer has an etch rate that is greater than the etch rate of the second insulating material layer when exposed to an etch composition. Portions of the first insulating material layer and the second insulating material layer are removed using at least the etch composition. Various types of structures (e.g., contacts, capacitors) are formed with use of the method.

Abstract translation: 蚀刻方法包括在第一绝缘材料层上在衬底组装表面上提供第一绝缘材料层和第二绝缘材料层。 当暴露于蚀刻组合物时，第一绝缘材料层具有大于第二绝缘材料层的蚀刻速率的蚀刻速率。 至少使用蚀刻组合物去除第一绝缘材料层和第二绝缘材料层的部分。 使用该方法形成各种类型的结构（例如，触点，电容器）。

公开(公告)号：US20040155274A1

公开(公告)日：2004-08-12

申请号：US10771042

申请日：2004-02-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Scott J. DeBoer ,  Whonchee Lee

IPC: H01L027/108

CPC classification number: H01L28/84 ,  H01L21/32134 ,  H01L28/75

Abstract: Capacitor structures and capacitors with edge zones that are substantially free of hemispherical grain silicon along the upper edges of the capacitor structures are disclosed. The resulting recessed hemispherical grain silicon layers reduce or prevent separation of particles from the hemispherical grain silicon layer during subsequent manufacturing processes, thereby reducing defects and increasing throughput. Also disclosed are methods of forming the capacitor structures and capacitors in which the silicon layer used to form the hemispherical grain silicon is selectively removed to provide an edge zone that is substantially free of hemispherical grain silicon.

公开(公告)号：US20020028563A1

公开(公告)日：2002-03-07

申请号：US09982294

申请日：2001-10-16

Applicant: Micron Technology, Inc.

Inventor： Scott J. DeBoer

IPC: H01L021/20

CPC classification number: H01L28/84 ,  H01L28/55 ,  H01L28/90

Abstract: Methods of manufacturing capacitor structures with edge zones that are substantially free of hemispherical grain silicon along the upper edges of the capacitor structures are disclosed. The resulting recessed hemispherical grain silicon layers reduce or prevent separation of particles from the hemispherical grain silicon layer during subsequent manufacturing processes, thereby reducing defects and increasing throughput. Among the methods of the present invention are methods of forming the capacitor structures in which the silicon layer used to form the hemispherical grain silicon is selectively doped. That selective doping provides an edge zone that does not convert to hemispherical grain silicon during manufacturing.

Abstract translation: 公开了沿着电容器结构的上边缘制造基本上不含半球形硅的边缘区的电容器结构的方法。 所产生的凹陷半球形晶粒硅层在随后的制造过程中减少或防止颗粒与半球形晶粒硅层分离，从而减少缺陷并提高生产量。 本发明的方法之一是形成电容器结构的方法，其中用于形成半球形晶粒硅的硅层被选择性掺杂。 该选择性掺杂提供了在制造期间不转化为半球形晶粒硅的边缘区域。