Invention Application
- Patent Title: Redundant latch circuit and associated methods
- Patent Title (中): 冗余锁存电路及相关方法
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Application No.: US10021150Application Date: 2001-10-30
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Publication No.: US20020095641A1Publication Date: 2002-07-18
- Inventor: Eric Noel Cartagena
- Applicant: Intersil Americas Inc.
- Applicant Address: US CA Irvine
- Assignee: Intersil Americas Inc.
- Current Assignee: Intersil Americas Inc.
- Current Assignee Address: US CA Irvine
- Main IPC: G06F011/18
- IPC: G06F011/18

Abstract:
A redundant latch circuit resistant to SEUs includes a plurality of latches, a majority voting circuit having inputs connected to the latch outputs, and a feedback reset circuit connected to the latch outputs and driving the latch reset inputs. The majority voting circuit indicates a set state for the redundant latch circuit based upon a majority of the latches being in the set state and indicating a reset state otherwise. The feedback reset circuit may have inputs connected to the outputs of the latches, and outputs connected to the reset inputs of the latches. The feedback reset circuit may switch at least one latch back to the reset state, from an SEU-induced change to the set state, when at least one other latch remains in the reset state to thereby provide resistance to SEUs.
Public/Granted literature
- US06504411B2 Redundant latch circuit and associated methods Public/Granted day:2003-01-07
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